fix typos (#2344)

COMPILE.TXT

@@ -17,7 +17,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 
 (0) Tailor Capstone to your need.
 
-  Out of all archtitectures supported by Capstone, if you just need several
+  Out of all architectures supported by Capstone, if you just need several
   selected archs, choose the ones you want to compile in by editing "config.mk"
   before going to next steps.
 

COMPILE_MSVC.TXT

@@ -19,7 +19,7 @@ or newer versions are required.
 
 (0) Tailor Capstone to your need.
 
-  Out of 9 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC,
+  Out of 9 architectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC,
   Sparc, SystemZ, X86 & XCore), if you just need several selected archs, choose
   the ones you want to compile in by opening Visual Studio solution "msvc\capstone.sln",
   then directly editing the projects "capstone_static" & "capstone_dll" for static

ChangeLog

@@ -424,7 +424,7 @@ Version 3.0.5: July 18th, 2018
 [ Core ]
 
 - Fix the include path for Android builds when building cstool.
-- Add posibility to disable universal build for Mac OS.
+- Add possibility to disable universal build for Mac OS.
 - cstool: Separate instruction bytes by spaces.
 - Fix code path of pkg-config in Cmake.
 - Update XCode project for XCode 9.1.
@@ -444,7 +444,7 @@ Version 3.0.5: July 18th, 2018
 
 [ ARM ]
 
-- Fix an integer overlow bug.
+- Fix an integer overflow bug.
 
 
 [ ARM64 ]
@@ -464,12 +464,12 @@ Version 3.0.5: July 18th, 2018
 
 [ Sparc ]
 
-- Fix an integer overlow bug.
+- Fix an integer overflow bug.
 
 
 [ SystemZ ]
 
-- Fix an integer overlow bug.
+- Fix an integer overflow bug.
 
 
 [ Python binding ]
@@ -961,7 +961,7 @@ Version 2.1: March 5th, 2014
 ----------------------------------
 Version 2.0: January 22nd, 2014
 
-Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes.
+Release 2.0 deprecates version 1.0 and brings a lot of crucial changes.
 
 [ API changes ]
 
@@ -973,7 +973,7 @@ Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes.
   cs_option().
 - New option CS_OPT_MEM allows to specify user-defined functions for dynamically
   memory management used internally by Capstone. This is useful to embed Capstone
-  into special environments such as kernel or firware.
+  into special environments such as kernel or firmware.
 - New API cs_support() can be used to check if this lib supports a particular
   architecture (this is necessary since we now allow to choose which architectures
   to compile in).
@@ -1009,7 +1009,7 @@ Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes.
 - Cython support has been added, which can further speed up over the default
   pure Python binding (up to 30% in some cases)
 - Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list)
-  to return succesfully disassembled instructions. This improves the performance
+  to return successfully disassembled instructions. This improves the performance
   and reduces memory usage.
 
 

MCInst.c

@@ -18,7 +18,7 @@
 
 void MCInst_Init(MCInst *inst)
 {
-	// unnecessary to initialize in loop . its expensive and inst->size shuold be honored
+	// unnecessary to initialize in loop . its expensive and inst->size should be honored
 	inst->Operands[0].Kind = kInvalid;
 	inst->Operands[0].ImmVal = 0;
 
@@ -89,7 +89,7 @@ unsigned MCInst_getNumOperands(const MCInst *inst)
 	return inst->size;
 }
 
-// This addOperand2 function doesnt free Op
+// This addOperand2 function doesn't free Op
 void MCInst_addOperand2(MCInst *inst, MCOperand *Op)
 {
 	assert(inst->size < MAX_MC_OPS);

MCInst.h

@@ -153,7 +153,7 @@ MCOperand *MCInst_getOperand(MCInst *inst, unsigned i);
 
 unsigned MCInst_getNumOperands(const MCInst *inst);
 
-// This addOperand2 function doesnt free Op
+// This addOperand2 function doesn't free Op
 void MCInst_addOperand2(MCInst *inst, MCOperand *Op);
 
 bool MCInst_isPredicable(const MCInstrDesc *MIDesc);

arch/AArch64/AArch64BaseInfo.h

@@ -815,7 +815,7 @@ typedef enum TOF {
 	/// an LDG instruction to obtain the tag value.
 	AArch64II_MO_TAGGED = 0x400,
 
-	/// MO_DLLIMPORTAUX - Symbol refers to "auxilliary" import stub. On
+	/// MO_DLLIMPORTAUX - Symbol refers to "auxiliary" import stub. On
 	/// Arm64EC, there are two kinds of import stubs used for DLL import of
 	/// functions: MO_DLLIMPORT refers to natively callable Arm64 code, and
 	/// MO_DLLIMPORTAUX refers to the original address which can be compared

arch/AArch64/AArch64InstPrinter.c

@@ -318,7 +318,7 @@ void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O)
 			(ImmR == 0 || ImmS < ImmR) &&
 			(AArch64_getFeatureBits(MI->csh->mode, AArch64_FeatureAll) ||
 			 AArch64_getFeatureBits(MI->csh->mode, AArch64_HasV8_2aOps))) {
-			// BFC takes precedence over its entire range, sligtly differently
+			// BFC takes precedence over its entire range, slightly differently
 			// to BFI.
 			int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32;
 			int LSB = (BitWidth - ImmR) % BitWidth;

arch/AArch64/AArch64Linkage.h

@@ -4,7 +4,7 @@
 #ifndef CS_AARCH64_LINKAGE_H
 #define CS_AARCH64_LINKAGE_H
 
-// Function defintions to call static LLVM functions.
+// Function definitions to call static LLVM functions.
 
 #include "../../MCDisassembler.h"
 #include "../../MCInst.h"

arch/AArch64/AArch64Mapping.c

@@ -247,7 +247,7 @@ void AArch64_init_cs_detail(MCInst *MI)
 /// So the only generic way to determine, if the memory access is in
 /// post-indexed addressing mode, is by search for "<membase>], #<memdisp>" in
 /// @p OS.
-/// Searching the asm string to determine such a property is enourmously ugly
+/// Searching the asm string to determine such a property is enormously ugly
 /// and wastes resources.
 /// Sorry, I know and do feel bad about it. But for now it works.
 static bool AArch64_check_post_index_am(const MCInst *MI, const SStream *OS) {
@@ -279,7 +279,7 @@ static void AArch64_check_updates_flags(MCInst *MI)
 	if (!detail_is_set(MI))
 		return;
 	cs_detail *detail = get_detail(MI);
-	// Implicity written registers
+	// Implicitly written registers
 	for (int i = 0; i < detail->regs_write_count; ++i) {
 		if (detail->regs_write[i] == 0)
 			break;

arch/AArch64/AArch64Mapping.h

@@ -14,7 +14,7 @@ typedef enum {
 #include "AArch64GenCSOpGroup.inc"
 } aarch64_op_group;
 
-// return name of regiser in friendly string
+// return name of register in friendly string
 const char *AArch64_reg_name(csh handle, unsigned int reg);
 
 // given internal insn id, return public instruction info

arch/ARM/ARMAddressingModes.h

@@ -7,7 +7,7 @@
 /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
 
 /* Only small edits allowed. */
-/* For multiple similiar edits, please create a Patch for the translator. */
+/* For multiple similar edits, please create a Patch for the translator. */
 
 /* Capstone's C++ file translator: */
 /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */

arch/ARM/ARMBaseInfo.c

@@ -7,7 +7,7 @@
 /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
 
 /* Only small edits allowed. */
-/* For multiple similiar edits, please create a Patch for the translator. */
+/* For multiple similar edits, please create a Patch for the translator. */
 
 /* Capstone's C++ file translator: */
 /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */

arch/ARM/ARMDisassembler.c

@@ -7,7 +7,7 @@
 /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
 
 /* Only small edits allowed. */
-/* For multiple similiar edits, please create a Patch for the translator. */
+/* For multiple similar edits, please create a Patch for the translator. */
 
 /* Capstone's C++ file translator: */
 /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
@@ -6411,7 +6411,7 @@ static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val,
 	// Inst. Reason is because MRRC2 stores to two
 	// registers so it's tablegen desc has has two
 	// outputs whereas MCRR doesn't store to any
-	// registers so all of it's operands are listed
+	// registers so all of its operands are listed
 	// as inputs, therefore the operand order for
 	// MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
 	// and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]

arch/ARM/ARMInstPrinter.c

@@ -7,7 +7,7 @@
 /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
 
 /* Only small edits allowed. */
-/* For multiple similiar edits, please create a Patch for the translator. */
+/* For multiple similar edits, please create a Patch for the translator. */
 
 /* Capstone's C++ file translator: */
 /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */

arch/ARM/ARMInstPrinter.h

@@ -7,7 +7,7 @@
 /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
 
 /* Only small edits allowed. */
-/* For multiple similiar edits, please create a Patch for the translator. */
+/* For multiple similar edits, please create a Patch for the translator. */
 
 /* Capstone's C++ file translator: */
 /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */

arch/ARM/ARMLinkage.h

@@ -4,7 +4,7 @@
 #ifndef CS_ARM_LINKAGE_H
 #define CS_ARM_LINKAGE_H
 
-// Function defintions to call static LLVM functions.
+// Function definitions to call static LLVM functions.
 
 #include "../../MCDisassembler.h"
 #include "../../MCInst.h"

arch/ARM/ARMMapping.c

@@ -531,7 +531,7 @@ static void ARM_add_not_defined_ops(MCInst *MI)
 }
 
 /// Unfortunately there is currently no way to easily extract
-/// informaion about the vector data usage (sign and width used).
+/// information about the vector data usage (sign and width used).
 /// See: https://github.com/capstone-engine/capstone/issues/2152
 void ARM_add_vector_data(MCInst *MI, arm_vectordata_type data_type)
 {
@@ -541,7 +541,7 @@ void ARM_add_vector_data(MCInst *MI, arm_vectordata_type data_type)
 }
 
 /// Unfortunately there is currently no way to easily extract
-/// informaion about the vector size.
+/// information about the vector size.
 /// See: https://github.com/capstone-engine/capstone/issues/2152
 void ARM_add_vector_size(MCInst *MI, unsigned size)
 {
@@ -2110,7 +2110,7 @@ void ARM_set_detail_op_sysop(MCInst *MI, int Val, arm_op_type type,
 	ARM_get_detail_op(MI, 0)->type = type;
 	switch (type) {
 	default:
-		assert(0 && "Unkown system operand type.");
+		assert(0 && "Unknown system operand type.");
 	case ARM_OP_SYSREG:
 		ARM_get_detail_op(MI, 0)->sysop.reg.mclasssysreg = Val;
 		break;

arch/ARM/ARMMapping.h

@@ -17,7 +17,7 @@ ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding);
 extern const ARMSysReg_MClassSysReg *
 ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding);
 
-// return name of regiser in friendly string
+// return name of register in friendly string
 const char *ARM_reg_name(csh handle, unsigned int reg);
 
 void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);

arch/Alpha/AlphaLinkage.h

@@ -4,7 +4,7 @@
 #ifndef CS_ALPHA_LINKAGE_H
 #define CS_ALPHA_LINKAGE_H
 
-// Function defintions to call static LLVM functions.
+// Function definitions to call static LLVM functions.
 
 #include "../../MCInst.h"
 #include "../../MCRegisterInfo.h"

arch/HPPA/HPPADisassembler.c

@@ -884,7 +884,7 @@ static void fill_alu_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode)
 			goto unit_cond;
 		case 0x2f:
 			push_str_modifier(hppa_ext, "i");
-			// fallthough
+			// fallthrough
 		case 0x26:
 		case 0x0e:
 		case 0x2e:
@@ -2857,7 +2857,7 @@ static bool decode_copr(const cs_struct *ud, MCInst *MI, uint32_t insn)
 			case 0x05:
 				CREATE_FPR_REG(MI, r1);
 				CREATE_FPR_REG(MI, t);
-				// fallthough
+				// fallthrough
 			case 0x00:
 				break;
 			default:
@@ -2882,7 +2882,7 @@ static bool decode_copr(const cs_struct *ud, MCInst *MI, uint32_t insn)
 			case 0x00:
 				CREATE_FPR_REG(MI, r1);
 				CREATE_FPR_REG(MI, r2);
-				// fallthough
+				// fallthrough
 			case 0x01:
 				break;
 			default:
@@ -3041,7 +3041,7 @@ static void fill_float_mods(uint32_t insn, uint32_t class, hppa_ext *hppa_ext,
 				return;
 			case 0x03:
 				push_str_modifier(hppa_ext, "t");
-				// fallthough
+				// fallthrough
 			case 0x02:
 				push_str_modifier(hppa_ext,
 						  float_format_names[sf]);

arch/M680X/M680XDisassembler.c

@@ -149,7 +149,7 @@ typedef struct insn_props {
 
 //////////////////////////////////////////////////////////////////////////////
 
-// M680X instuctions have 1 up to 8 bytes (CPU12: MOVW IDX2,IDX2).
+// M680X instructions have 1 up to 8 bytes (CPU12: MOVW IDX2,IDX2).
 // A reader is needed to read a byte or word from a given memory address.
 // See also X86 reader(...)
 static bool read_byte(const m680x_info *info, uint8_t *byte, uint16_t address)
@@ -627,7 +627,7 @@ typedef struct insn_desc {
 	uint16_t insn_size;
 } insn_desc;
 
-// If successfull return the additional byte size needed for M6809
+// If successful return the additional byte size needed for M6809
 // indexed addressing mode (including the indexed addressing post_byte).
 // On error return -1.
 static int get_indexed09_post_byte_size(const m680x_info *info,
@@ -681,7 +681,7 @@ static int get_indexed09_post_byte_size(const m680x_info *info,
 	return 1;
 }
 
-// If successfull return the additional byte size needed for CPU12
+// If successful return the additional byte size needed for CPU12
 // indexed addressing mode (including the indexed addressing post_byte).
 // On error return -1.
 static int get_indexed12_post_byte_size(const m680x_info *info,
@@ -750,7 +750,7 @@ static bool is_tfm_reg_valid(const m680x_info *info, uint8_t reg_nibble)
 	return reg_nibble <= 4;
 }
 
-// If successfull return the additional byte size needed for CPU12
+// If successful return the additional byte size needed for CPU12
 // loop instructions DBEQ/DBNE/IBEQ/IBNE/TBEQ/TBNE (including the post byte).
 // On error return -1.
 static int get_loop_post_byte_size(const m680x_info *info, uint16_t address)
@@ -772,7 +772,7 @@ static int get_loop_post_byte_size(const m680x_info *info, uint16_t address)
 	return 2;
 }
 
-// If successfull return the additional byte size needed for HD6309
+// If successful return the additional byte size needed for HD6309
 // bit move instructions BAND/BEOR/BIAND/BIEOR/BIOR/BOR/LDBT/STBT
 // (including the post byte).
 // On error return -1.
@@ -1885,7 +1885,7 @@ static unsigned int m680x_disassemble(MCInst *MI, m680x_info *info,
 
 		access_mode = g_insn_props[info->insn].access_mode;
 
-		// Fix for M6805 BSET/BCLR. It has a differnt operand order
+		// Fix for M6805 BSET/BCLR. It has a different operand order
 		// in comparison to the M6811
 		if ((info->cpu->insn_cc_not_modified[0] == info->insn) ||
 			(info->cpu->insn_cc_not_modified[1] == info->insn))

arch/M68K/M68KDisassembler.c

@@ -3526,7 +3526,7 @@ static void build_regs_read_write_counts(m68k_info *info)
 		// first operand is always read
 		update_op_reg_list(info, &info->extension.operands[0], 0);
 
-		// remaning write
+		// remaining write
 		for (i = 1; i < info->extension.op_count; ++i)
 			update_op_reg_list(info, &info->extension.operands[i], 1);
 	}

arch/Mips/MipsDisassembler.c

@@ -365,7 +365,7 @@ void Mips_init(MCRegisterInfo *MRI)
 }
 
 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
-/// according to the given endianess.
+/// according to the given endianness.
 static void readInstruction16(unsigned char *code, uint32_t *insn,
 		bool isBigEndian)
 {
@@ -377,7 +377,7 @@ static void readInstruction16(unsigned char *code, uint32_t *insn,
 }
 
 /// readInstruction - read four bytes from the MemoryObject
-/// and return 32 bit word sorted according to the given endianess
+/// and return 32 bit word sorted according to the given endianness
 static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips)
 {
 	// High 16 bits of a 32-bit microMIPS instruction (where the opcode is)

arch/Mips/MipsMapping.h

@@ -6,7 +6,7 @@
 
 #include "capstone/capstone.h"
 
-// return name of regiser in friendly string
+// return name of register in friendly string
 const char *Mips_reg_name(csh handle, unsigned int reg);
 
 // given internal insn id, return public instruction info