Optimize tests and fix imm in map & null deref due invalid pointer.

capstone-engine · Sep 3, 2024 · e231289 · e231289
1 parent 0953b79
commit e231289
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Showing 118 changed files with 115,695 additions and 695 deletions.
diff --git a/.gitignore b/.gitignore
@@ -143,7 +143,7 @@ cstool/cstool
 android-ndk-*
 
 # python virtual env
-.venv/
+.ven*/
 
 # Auto-sync files
 suite/auto-sync/src/autosync.egg-info

diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c
@@ -63,10 +63,11 @@ bool Mips_getFeatureBits(unsigned int mode, unsigned int feature)
 	case Mips_FeatureFP64Bit:
 		return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS3 | 
 						CS_MODE_MIPS4 | CS_MODE_MIPS5 | 
-						CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | 
-						CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | 
-						CS_MODE_MIPS64R6 | CS_MODE_OCTEON | 
-						CS_MODE_OCTEONP);
+						CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 |
+						CS_MODE_MIPS32R5 | CS_MODE_MIPS64 |
+						CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 |
+						CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 |
+						CS_MODE_OCTEON | CS_MODE_OCTEONP);
 	case Mips_FeatureNaN2008:
 		return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS64R6);
 	case Mips_FeatureAbs2008:
@@ -835,8 +836,8 @@ static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, uint32_t insn,
 {
        uint32_t Rs = fieldFromInstruction_4(insn, 16, 5);
        uint32_t Imm = fieldFromInstruction_4(insn, 0, 16);
-       MCOperand_CreateReg0(MI, (getReg(Decoder, Mips_GPR64RegClassID, Rs)));
-       MCOperand_CreateReg0(MI, (getReg(Decoder, Mips_GPR64RegClassID, Rs)));
+       MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs)));
+       MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs)));
        MCOperand_CreateImm0(MI, (Imm));
 
        return MCDisassembler_Success;
@@ -848,8 +849,8 @@ static DecodeStatus DecodeDAHIDATI(MCInst *MI, uint32_t insn, uint64_t Address,
  {
        uint32_t Rs = fieldFromInstruction_4(insn, 21, 5);
        uint32_t Imm = fieldFromInstruction_4(insn, 0, 16);
-       MCOperand_CreateReg0(MI, (getReg(Decoder, Mips_GPR64RegClassID, Rs)));
-       MCOperand_CreateReg0(MI, (getReg(Decoder, Mips_GPR64RegClassID, Rs)));
+       MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs)));
+       MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs)));
         MCOperand_CreateImm0(MI, (Imm));
 
         return MCDisassembler_Success;

diff --git a/arch/Mips/MipsGenCSMappingInsnOp.inc b/arch/Mips/MipsGenCSMappingInsnOp.inc
diff --git a/arch/Mips/MipsInstPrinter.c b/arch/Mips/MipsInstPrinter.c
@@ -107,6 +107,7 @@ static const char *MipsFCCToString(Mips_CondCode CC)
 		return "ngt";
 	}
 	assert(0 && "Impossible condition code!");
+	return "";
 }
 
 const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName);
@@ -121,8 +122,24 @@ static void printRegName(MCInst *MI, SStream *OS, MCRegister Reg)
 }
 
 void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O) {
-	if (!printAliasInstr(MI, Address, O) && !printAlias4(MI, Address, O))
+	bool useAliasDetails = map_use_alias_details(MI);
+	if (!useAliasDetails) {
+		SStream_Close(O);
 		printInstruction(MI, Address, O);
+		SStream_Open(O);
+		map_set_fill_detail_ops(MI, false);
+	}
+
+	if (printAliasInstr(MI, Address, O) ||
+		printAlias4(MI, Address, O)) {
+		MCInst_setIsAlias(MI, true);
+	} else {
+		printInstruction(MI, Address, O);
+	}
+
+	if (!useAliasDetails) {
+		map_set_fill_detail_ops(MI, true);
+	}
 }
 
 void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
@@ -520,7 +537,7 @@ static void printPCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O)
 
 const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName)
 {
-	if (RegNo >= MIPS_REG_ENDING) {
+	if (!RegNo || RegNo >= MIPS_REG_ENDING) {
 		return NULL;
 	}
 	if (noRegName) {