AArch64: movn w0, #0, lsl #16 and movz w0, #0, lsl #16 are indistinguishable

[thestr4ng3r]

On next (31af3c3):

florian-macbook:capstone florian$ cstool -d arm64 0000a012
 0  00 00 a0 12  movn	w0, #0, lsl #16
	ID: 488 (mov)
	op_count: 2
		operands[0].type: REG = w0
		operands[0].access: READ | WRITE
		operands[1].type: IMM = 0x0
		operands[1].access: READ
			Shift: type = 1, value = 16
	Registers read: w0
	Registers modified: w0

florian-macbook:capstone florian$ cstool -d arm64 0000a052
 0  00 00 a0 52  movz	w0, #0, lsl #16
	ID: 488 (mov)
	op_count: 2
		operands[0].type: REG = w0
		operands[0].access: READ | WRITE
		operands[1].type: IMM = 0x0
		operands[1].access: READ
			Shift: type = 1, value = 16
	Registers read: w0
	Registers modified: w0

Notice how both instructions have the exact same id and details. However their semantics are different (write 0xffffffff vs. write 0).

Some context:

The #0, lsl #16 operands are an edge case of both instructions. In other cases, for example movn w0, #2, lsl #16 (4000a012) it gets disassembled as e.g. mov w0, #-0x20001 where the final value is already resolved and also reflected like this in the details, so there it's fine.
See also the condition in the reference manual: