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AArch64: Some SVE memory operands not set correctly #2055
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…tion in `AArch64InstPrinter.c` that is very similar to the one made by `printOperand` in the same file. If we are in the middle of printing a memory operand, the operand type is no longer changed to type REG. Instead, a base or index register is set.
Will fix it in #2026 typedef struct aarch64_op_sme {
aarch64_sme_op_type type; ///< AArch64_SME_OP_TILE, AArch64_SME_OP_TILE_VEC, AArch64_SME_OP_ACC_MATRIX
aarch64_reg tile; ///< Matrix tile register
aarch64_reg slice_reg; ///< slice index reg
int8_t slice_offset; ///< slice index offset
bool is_vertical; ///< Flag if slice is vertical or horizontal
} aarch64_op_sme; |
Wow very excited for the updates in Issue #2026! I don't currently see a need for something different than the original arm64_op_mem/aarch64_op_mem, at least for the SVE instructions. The SVE addressing modes can fit neatly into the struct: Scalar + immediate: The only thing missing is the memory data type (e.g. ld1w loads words before extending). I did implement a fix in my own repo and reran the examples above. I hope this helps you add to your own tests.
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Nice! Can you give an example for |
Sure:
Note that the access is not reported for these operands and the final registers read/written is incomplete. Register z1 should be written, for instance. This is mentioned in other issues (#1911). I don't know if you plan to fix that in #2026. |
Yes, since we generate everything now, this data will be part of every architecture refactored to auto-sync.
22 Jun 2023 14:32:56 accauble ***@***.***>:
…
Sure:
*$ ./cstool -d arm64be "85 62 40 21"
0 85 62 40 21 ld1w {z1.s}, p0/z, [x1, z2.s, sxtw #2]
ID: 457 (ld1w)
op_count: 3
operands[0].type: REG = z1
Vector Arrangement Specifier: 0xb
operands[1].type: REG = p0
operands[2].type: MEM
operands[2].mem.base: REG = x1
operands[2].mem.index: REG = z2
Shift: type = 1, value = 2
Ext: 7
Registers read: x1 z2
**$ ~./cstool -d arm64be "a5 42 40 21"
0 a5 42 40 21 ld1w {z1.s}, p0/z, [x1, x2, lsl #2]
ID: 457 (ld1w)
op_count: 3
operands[0].type: REG = z1
Vector Arrangement Specifier: 0xb
operands[1].type: REG = p0
operands[2].type: MEM
operands[2].mem.base: REG = x1
operands[2].mem.index: REG = x2
Shift: type = 1, value = 2
Registers read: x1 x2
*
Note that the access is not reported for these operands and the final registers read/written is incomplete. Register z1 should be written, for instance. This is mentioned in other issues (#1911[#1911]). I don't know if you plan to fix that in #2026[#2026].
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Description
The operands for some SVE memory instructions (at least those that are "vector plus immediate" addressing modes) are not set correctly. Where there should be a memory type, it is labeled as a register type. The immediate should be marked as the displacement, but it is stored as an immediate in the next operand, which is labeled as INVALID.
Examples
Using commit d0ef88a on the
next
branch:In the above, the string is correct, but operand 2 should be of type mem and have a displacement of 8.
A similar example, but a different instruction:
Again, the string is correct but the second operand should be a memory operand.
Suggested Solution
In
AArch64InstPrinter.c:printSVERegOp
, theMI->csh>doing_mem
flag could be checked, and operand information could be set accordingly. This would be very similar to theprintOperand
function in the same file:The text was updated successfully, but these errors were encountered: