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AArch64 armv9.2 update #1907

Merged
merged 12 commits into from
Oct 6, 2022
Merged

AArch64 armv9.2 update #1907

merged 12 commits into from
Oct 6, 2022

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FinnWilkinson
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@FinnWilkinson FinnWilkinson commented Aug 1, 2022 •
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The work done is this pull request updates the AArch64 disassembler to Armv9.2-a; based upon LLVM 14.0.5.

Detailed below is a summary of changes made :

  • New .inc files for AArch64 architecture
  • Implemented new decode and printing functions as required for AArch64
  • Updated relevant enums in Arm64.h
    • System and Operand Registers, ARM64 instructions, ARM64 Groups, System Operands,
  • Reformatted many of the synctool python scripts to work with LLVM 14's changes
  • Created a new struct and added to instruction_object to expose the SVCR value (used by SME)
  • Created a new SVCR print-out to make clear which sys_register is being updated and which bits are changed
    • In the SVCR register, bits 0 and 1 are used to signify if the ZA and SM context modes respectively are enabled/disabled
  • Updated the AArch64 tablegen source files to LLVM 14.0.5
  • Few minor bug fixes

Edit :

  • Created new struct arm64_op_sme_index and added to cs_arm64_op to more accuratly represent SME instruction operands that have index of the form [wn, #imm].
    • set_sme_index and relevant print functions were added so that the appropriate SME instructions use this new struct rather than arm64_op_mem

I am sure that this PR will be incomplete, so please let me know of any changes or fixes that should be made!

@kabeor
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kabeor commented Aug 4, 2022

Hi, plz check ci result.

@FinnWilkinson
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To note - the Python CI tests are segfaulting and failing various tests, despite displaying test pass

@aquynh
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aquynh commented Aug 4, 2022 via email

@FinnWilkinson
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please can you clean up the PR, as it includes a lot of old commits?

Yes of course. After fixing the CI test issues, I will squash commits into logical blocks to reduce and clean up the PR.

@FinnWilkinson
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One of the failing tests is due to the change made in #1655 being reverted. This was done as it was noticed that access types were not always correct, and I was getting segFaults when using Capstone with an external project.

Whilst the fix from #1655 does correct the access types for aliased cmp instructions, it collects incorrect access types for others. In the case of ldrsw x2, [x0], #4 (HEX= 0x024480B8) the access types should be: x2=WRITE, [x0]=READ | WRITE, however with the change from #1655 the access types are x2=READ | WRITE, [x0]=READ | WRITE.

@kabeor @aquynh please advise on whether the change made in #1655 should be reverted in this PR (and the corresponding test in issues.cs commented out) or if said change should remain and be fixed at a later date?

@kabeor
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kabeor commented Aug 11, 2022

Hi, thanks for your contribution. I think reverting it temporary in your code and report this issue is a good way for now, we can focus on that after merge this pr.

@FinnWilkinson FinnWilkinson mentioned this pull request Aug 11, 2022
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@FinnWilkinson
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Appologies for the delay on this PR. I aim to fix the latest CIFuzz error and tidy the commit history this week

@FinnWilkinson
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Hi @kabeor, please could the fuzzing tests and other workflows be re-run? Thanks

@kabeor
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kabeor commented Sep 22, 2022

Hi @kabeor, please could the fuzzing tests and other workflows be re-run? Thanks

Hi, fuzzing test not pass, plz check it:)

@FinnWilkinson
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Hi, fuzzing test not pass, plz check it:)

Sorry for the delay, I have re-worked the logic which was causing the address sanitizer error, so hopefully the issue has now been resolved!

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kabeor commented Sep 28, 2022

Still failed😢, plz check again.

@FinnWilkinson
Updated include/llvm files in synctools to LLVM 14.0.5.
dced482
@FinnWilkinson
Updated synctools/tablegen/AArch64 files to LLVM 14.0.5.
44ba50b
@FinnWilkinson
Changed AArch64 filegen order to resepct inter-file dependancies.
3bb4488 
make arm64 needs to be performed before AArch64GenRegisterV.inc is generated.
@FinnWilkinson
Updated suite/synctools/.gitignore to ignore generated insn_list.txt …
d94535d 
…file.
@FinnWilkinson
Updated synctool scripts to extract new functions and match type/form…
34749cf 
…atting changes in LLVM 14.0.5 tablegen files.

 - asmwriter.py : As well as new functions, recognition of new SME index printing was added. The printAliasInstr function also required a re-write to match its counter-part and changes in logic in LLVM 14.0.5
 - disassemblertables-arch.py : Minor type changes for some functions, as well as adding support for new SME decode functions.
 - mapping_insn-arch.py : Minor change to correct incorrect instruction aliasing in generated AArch64MappingInsn.inc etc.
 - registerinfo.py : minor change to reflect change in LLVM 14.0.5
 - systemoperand.py : corrected minor type changes made in LLVM 14.0.5 and added extraction of SVCR, BTI, DBnXS lists and encoding functions.
@FinnWilkinson
Generated new Armv9.2 AArch64 .inc files from LLVM 14.0.5
74be6d0
@FinnWilkinson
Updated AArch64 Disassembler.
fdbb158 
Added new decode functions, mainly for SME matrix operands and SVCR sys
register, as well as updating existing decode functions which have seen
changes in LLVM 14.0.5.

The _getInstruction function has also been updated to its LLVM 14.0.5
counterpart; with a new switch case for adding implicit operands to the
relevant SME instructions.
@FinnWilkinson
Updated AArch64 BaseInfo.h and Mapping.c to refelct Armv9.2 architect…
8ef3f91 
…ural changes and .inc file changes.
@FinnWilkinson
Updated arm64.h to refelct changes to architecture in Armv9.2 and LLVM
d090c76 
14.0.5, and introduced new arm64 operand types.

New operand type for svcr MSR/MRS/SMSTART/SMSTOP instructions to
facilitate easier cstool printing.

New operand type for SME instructions with a matrix register that is
indexed.
@FinnWilkinson
Updated AArch64 Instruction Printer to support new Armv9.2 instructions.
a29498b 
Implemented new functions present in LLVM 14.0.5 for any new instruction
type in Armv9.2; mainly SME / Matrix printing functions.

New set_sme_index function added (called from AArch64GenAsmWriter.inc)
to correctly add operands to new sme_index operand type. Doing_SME_Index
bool added to cs_struct to indicate when operands should be added to
sme_index type.

Functionality added to support SMSTART/SMSTOP aliases.
@FinnWilkinson
Added cstool printing cases for new AArch64 operand types SVCR and SM…
489a4cd 
…E_Index.
@FinnWilkinson
Updated AArch64 tests to match corrections to instruction aliases.
f5a633d 
Issue 1653 test commented out as the change made for this issue was reverted due to it being incomplete for all instructions. New issue capstone-engine#1911 has been opened to document that the original issue needs re-addressing.
@FinnWilkinson
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Have solved fuzzing errors and cleaned up the commit history. Please see and let me know if it is all satisfactory!

@kabeor
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kabeor commented Oct 6, 2022

Very awesome! Thanks for your great contribution. Merged.
We need keeping our eyes on #1655 next step.

@kabeor kabeor merged commit 662bb3f into capstone-engine:next Oct 6, 2022
@FinnWilkinson FinnWilkinson mentioned this pull request Oct 24, 2022
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@wideglide
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It appears this PR broke something in the python bindings? #1929

This was referenced Oct 31, 2022
Closed
Merged
@FinnWilkinson FinnWilkinson mentioned this pull request Mar 7, 2024
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4 participants
@FinnWilkinson @kabeor @aquynh @wideglide