FPGA code generation improvents

[carlosedp]

The core generation for FPGA fails due to:

• Memory initialization is generated only inside the ifndef SYNTHESIS block #4752 - Memory initialization is generated only inside the ifndef SYNTHESIS block llvm/circt#4752 -> Fixed by Memory initialization is generated only inside the ifndef SYNTHESIS block llvm/circt#4752 (comment)
• Synthesizing generated files with Yosys threw a unexpected TOK_AUTOMATIC error #4751 - Synthesizing generated files with Yosys threw a unexpected TOK_AUTOMATIC error llvm/circt#4751

The ideal scenario would be fixing:

• Chisel design with inline blackbox verilog generates .sv output with filenames at the end #4249 - Chisel design with inline blackbox verilog generates .sv output with filenames at the end llvm/circt#4249
• Feature Request: Provide a similar --target:fpga behavior for FPGA-suited targets #4230 - [FIRRTL] Feature Request: Provide a similar --target:fpga behavior for FPGA-suited targets llvm/circt#4230

That would lead to having a single SV file without the need to split files and a flag to enable memory initialization for synthesis cleaning-up the chiselv.core file (Have a single Toplevel.sv and removing the --split-verilog params).

[carlosedp]

After the hack into firtool to correctly initialize the memory outside the ifndef, the reset in the core does not behave as expected. Need to investigate further.