Chisel design with inline blackbox verilog generates .sv output with filenames at the end

[carlosedp]

On my Chisel design, I have some modules that use inline blackbox Verilog code (Eg. https://github.com/carlosedp/chiselv/blob/dd33dc558fb703adc95fd2c719367e5f2dc0e709/chiselv/src/GPIO.scala#L49)

When going thru firtool, the generated .sv file have the "blackboxed" verilog code inlined (which is neat) but it appended the file names from my blackboxes to the end of the file:

Commenting-out those two lines, make Verilator compile it fine.

I was pointed to use --split-verilog -o=generated to generate separate .sv files to each module but then my Toplevel module file ended blank (which might be or not another issue).

[carlosedp]

I believe even having the split files option, this is still a bug since the two resource files were correctly inlined in the generated SV file but the filenames were appended to the end.

[carlosedp]

Bump. Any feedback if this is supposed to be a bug and the filelist output could be suppressed from the output SV?

I could look into providing a PR with some guidance on where to look :)

[darthscsi]

Yes, if the modules existed, they should not be in a file list, though much of that is from maintaining past chisel behavior (which is woofully unspecified for lots of combinations of blackblox).

That said, single-file output is purely for writing testcases, it will not produce valid verilog in many cases. I intend to hide it as an option at some point.

[carlosedp]

Closing thoughts here... so I understand the '-o' option to output a single-file .sv plans to be deprecated and the way to go is keep generating split files for each module, right?
If not, I could take a look into excluding from the single file output, everything that is a filelist (*.f). I just need some guidance on it.
Thanks!