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726 Open 1,448 Closed
726 Open 1,448 Closed
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Issues list

[HWToLLVM] Don't crash on OOB accesses
#8214 opened Feb 10, 2025 by maerhart
[arcilator] Install configuration missing for arcilator-runtime.h Arc Involving the `arc` dialect
#8212 opened Feb 10, 2025 by maerhart
[MooreToCore]Unexpected observed values in llhd.wait. Moore
#8211 opened Feb 8, 2025 by hailongSun2000
[circt-bmc] Add support for verif.symbolic_value verif
#8197 opened Feb 6, 2025 by fabianschuiki
2
Documentation on Analyzing Circuits with Python Bindings
#8195 opened Feb 5, 2025 by tymcauley
1
[RTG][Elaboration] Each virtual register should only be materialized once and every user should use it bug Something isn't working RTG Involving the `rtg` dialect
#8193 opened Feb 5, 2025 by maerhart
[MooreToCore] Crash when getting values to observe Moore
#8176 opened Feb 3, 2025 by maerhart
@hailongSun2000
6
[ImportVerilog] Crash on ordering-methods-reverse test bug Something isn't working ImportVerilog
#8173 opened Feb 2, 2025 by fabianschuiki
[MooreToCore] Out-of-bounds moore.extract lowered incorrectly Moore
#8163 opened Jan 31, 2025 by maerhart
1
[RTG][Elaboration] Malloc unique label values RTG Involving the `rtg` dialect
#8161 opened Jan 31, 2025 by maerhart
[RTG][Elaboration] Malloc virtual register values RTG Involving the `rtg` dialect
#8160 opened Jan 31, 2025 by maerhart
[FIRRTL] LowerToHW discards private modules FIRRTL Involving the `firrtl` dialect
#8153 opened Jan 30, 2025 by fabianschuiki
[circt-test] sby runner doesn't fail if module doesn't exist bug Something isn't working
#8145 opened Jan 29, 2025 by fabianschuiki
Firtool and aarch64
#8135 opened Jan 28, 2025 by timmerrifield
2
[MooreToCore] Support moore.array_create good first issue Good for newcomers Moore
#8128 opened Jan 25, 2025 by fabianschuiki
@manojks1999
1
[FIRRTL] Intrinsic documentation: Ports and Direction tables are bit confusing documentation Improvements or additions to documentation FIRRTL Involving the `firrtl` dialect
#8111 opened Jan 22, 2025 by dtzSiFive
Status and getting started
#8099 opened Jan 20, 2025 by ecstrema
2
[FIRRTL] more strict connect semantic
#8069 opened Jan 12, 2025 by sequencer
1
[LLHD][Arc] Indexing and slicing lowering from Verilog to LLVM IR
#8065 opened Jan 10, 2025 by AndreyVV-100
3
Add custom parser for SMT bitvector width SMT
#8064 opened Jan 10, 2025 by TaoBi22
@TaoBi22
[SMT] Implicit overflow when parsing !smt.bv type? bug Something isn't working SMT
#8062 opened Jan 10, 2025 by maerhart
[FIRRTL] Incorrect directory behavior when testbench involved bug Something isn't working FIRRTL Involving the `firrtl` dialect
#8061 opened Jan 10, 2025 by seldridge
[Feature Proposal] Add a pass on hw.module to remove certain modules from the hierarchy and recursively expose its IO
#8060 opened Jan 9, 2025 by CircuitCoder
[Python] MacOS wheel builds fail after successfully building and installing CIRCTPythonModules. Python Python bindings
#8054 opened Jan 9, 2025 by mikeurbach
[FIRRTL] FIRRTLExporter name collides when operations having same name attr
#8027 opened Jan 3, 2025 by sequencer
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