[ImportVerilog] Crash on ordering-methods-reverse test

[fabianschuiki]

Running circt-verilog on https://chipsalliance.github.io/sv-tests-results/?v=circt_verilog+7.4.2+ordering-methods-reverse causes a crash.

module top ();

string s[] = { "hello", "sad", "world" };

initial begin
	$display(":assert: (('%s' == 'hello') and ('%s' == 'sad') and ('%s' == 'world'))",
		s[0], s[1], s[2]);
	s.reverse;
	$display(":assert: (('%s' == 'world') and ('%s' == 'sad') and ('%s' == 'hello'))",
		s[0], s[1], s[2]);
end

endmodule

circt-verilog -I /root/sv-tests/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods --timescale=1ns/1ns --single-unit --top=top [tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv](https://chipsalliance.github.io/sv-tests-results/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv.html)
[tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:18:16](https://chipsalliance.github.io/sv-tests-results/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv.html#l-18): error: expression of type '!moore.string' cannot be cast to a simple bit vector
string s[] = { "hello", "sad", "world" };
               ^
[tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:18:25](https://chipsalliance.github.io/sv-tests-results/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv.html#l-18): error: expression of type '!moore.string' cannot be cast to a simple bit vector
string s[] = { "hello", "sad", "world" };
                        ^
[tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:18:32](https://chipsalliance.github.io/sv-tests-results/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv.html#l-18): error: expression of type '!moore.string' cannot be cast to a simple bit vector
string s[] = { "hello", "sad", "world" };
                               ^
PLEASE submit a bug report to https://github.com/llvm/circt and include the crash backtrace.
Stack dump:
0.	Program arguments: circt-verilog -I /root/sv-tests/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods --timescale=1ns/1ns --single-unit --top=top [tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv](https://chipsalliance.github.io/sv-tests-results/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv.html)
Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var `LLVM_SYMBOLIZER_PATH` to point to it):
0  circt-verilog 0x000055976388cb47
1  circt-verilog 0x000055976388a9ee
2  circt-verilog 0x000055976388d21a
[...]