✅ Update Unit Tests and Exclude Long-Running Tests in Debug Mode Usin…

…g ``NDEBUG`` (#574) * ✨ Configure CMake for Release-Only Unit Tests by Adding Build-Specific Macros * 🎨 Incorporated pre-commit fixes * 🎨 implement Marcel's feedback. * 🎨 Incorporated pre-commit fixes --------- Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
cda-tum · Nov 15, 2024 · 34de9f1 · 34de9f1
1 parent 8bc151f
commit 34de9f1
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Showing 4 changed files with 51 additions and 34 deletions.
diff --git a/test/algorithms/physical_design/design_sidb_gates.cpp b/test/algorithms/physical_design/design_sidb_gates.cpp
@@ -406,13 +406,16 @@ TEST_CASE("Design NOR Bestagon shaped gate on H-Si 111", "[design-sidb-gates]")
                 cell<sidb_111_cell_clk_lyt_siqad>>::design_sidb_gates_mode::AUTOMATIC_EXHAUSTIVE_GATE_DESIGNER,
             {{10, 13, 0}, {14, 17, 0}},
             3};
-
+// to save runtime in the CI, this test is only run in RELEASE mode
+#ifdef NDEBUG
         SECTION("all design")
         {
             const auto found_gate_layouts = design_sidb_gates(lyt, std::vector<tt>{create_nor_tt()}, params);
             REQUIRE(found_gate_layouts.size() == 14);
             CHECK(found_gate_layouts.front().num_cells() == lyt.num_cells() + 3);
         }
+#endif
+
         SECTION("terminate after first solution is found")
         {
             params.termination_cond = design_sidb_gates_params<
@@ -422,7 +425,8 @@ TEST_CASE("Design NOR Bestagon shaped gate on H-Si 111", "[design-sidb-gates]")
             CHECK(found_gate_layouts.front().num_cells() == lyt.num_cells() + 3);
         }
     }
-
+// to save runtime in the CI, this test is only run in RELEASE mode
+#ifdef NDEBUG
     SECTION("Exhaustive Generation, forbidding kinks")
     {
         const design_sidb_gates_params<cell<sidb_111_cell_clk_lyt_siqad>> params{
@@ -437,6 +441,7 @@ TEST_CASE("Design NOR Bestagon shaped gate on H-Si 111", "[design-sidb-gates]")
         REQUIRE(found_gate_layouts.size() == 3);
         CHECK(found_gate_layouts.front().num_cells() == lyt.num_cells() + 3);
     }
+#endif
 
     SECTION("Exhaustive Generation, QuickCell")
     {
@@ -467,6 +472,8 @@ TEST_CASE("Design NOR Bestagon shaped gate on H-Si 111", "[design-sidb-gates]")
     }
 }
 
+// to save runtime in the CI, this test is only run in RELEASE mode
+#ifdef NDEBUG
 TEST_CASE("Design Bestagon shaped CX gate with QuickCell", "[design-sidb-gates]")
 {
     const auto lyt = blueprints::two_input_two_output_bestagon_skeleton<sidb_100_cell_clk_lyt_siqad>();
@@ -526,3 +533,4 @@ TEST_CASE("Design AND gate with input left and output top-right with QuickCell (
               operational_status::OPERATIONAL);
     }
 }
+#endif
diff --git a/test/algorithms/simulation/sidb/critical_temperature.cpp b/test/algorithms/simulation/sidb/critical_temperature.cpp
@@ -562,6 +562,8 @@ TEMPLATE_TEST_CASE("Test critical_temperature function, using offset coordinates
     }
 }
 
+// to save runtime in the CI, this test is only run in RELEASE mode
+#ifdef NDEBUG
 TEMPLATE_TEST_CASE("Critical temperature of Bestagon CX, QuickExact", "[critical-temperature], [quality]",
                    sidb_100_cell_clk_lyt_siqad, cds_sidb_100_cell_clk_lyt_siqad)
 {
@@ -669,3 +671,4 @@ TEMPLATE_TEST_CASE("Critical temperature of Bestagon half adder gate, QuickExact
                Catch::Matchers::WithinAbs(0.00, 0.01));
     CHECK_THAT(std::abs(ct - 0.40), Catch::Matchers::WithinAbs(0.00, 0.01));
 }
+#endif
diff --git a/test/algorithms/simulation/sidb/is_operational.cpp b/test/algorithms/simulation/sidb/is_operational.cpp
@@ -240,6 +240,40 @@ TEST_CASE("AND gate with bestagon structure and kink state at right input wire f
     }
 }
 
+TEST_CASE("BDL wire", "[is-operational]")
+{
+    using layout = sidb_cell_clk_lyt_siqad;
+
+    layout lyt{{24, 0}, "BDL wire"};
+
+    lyt.assign_cell_type({0, 0, 0}, sidb_technology::cell_type::INPUT);
+    lyt.assign_cell_type({3, 0, 0}, sidb_technology::cell_type::INPUT);
+
+    lyt.assign_cell_type({6, 0, 0}, sidb_technology::cell_type::NORMAL);
+    lyt.assign_cell_type({8, 0, 0}, sidb_technology::cell_type::NORMAL);
+
+    lyt.assign_cell_type({12, 0, 0}, sidb_technology::cell_type::NORMAL);
+    lyt.assign_cell_type({14, 0, 0}, sidb_technology::cell_type::NORMAL);
+
+    lyt.assign_cell_type({18, 0, 0}, sidb_technology::cell_type::OUTPUT);
+    lyt.assign_cell_type({20, 0, 0}, sidb_technology::cell_type::OUTPUT);
+
+    // output perturber
+    lyt.assign_cell_type({24, 0, 0}, sidb_technology::cell_type::NORMAL);
+
+    const sidb_100_cell_clk_lyt_siqad lat{lyt};
+
+    sidb_simulation_parameters sim_params{};
+
+    sim_params.base = 2;
+
+    const is_operational_params params{sim_params};
+
+    CHECK(is_operational(lyt, std::vector<tt>{create_id_tt()}, params).first == operational_status::OPERATIONAL);
+}
+
+// to save runtime in the CI, this test is only run in RELEASE mode
+#ifdef NDEBUG
 TEST_CASE("flipped CX bestagon gate", "[is-operational]")
 {
     const auto lyt = blueprints::crossing_bestagon_shape_input_down_output_up<sidb_cell_clk_lyt_siqad>();
@@ -365,35 +399,4 @@ TEST_CASE("is operational check for Bestagon half adder", "[is-operational], [qu
                        is_operational_params{sidb_simulation_parameters{2, -0.25}, sidb_simulation_engine::QUICKEXACT})
             .first == operational_status::NON_OPERATIONAL);
 }
-
-TEST_CASE("BDL wire", "[is-operational]")
-{
-    using layout = sidb_cell_clk_lyt_siqad;
-
-    layout lyt{{24, 0}, "BDL wire"};
-
-    lyt.assign_cell_type({0, 0, 0}, sidb_technology::cell_type::INPUT);
-    lyt.assign_cell_type({3, 0, 0}, sidb_technology::cell_type::INPUT);
-
-    lyt.assign_cell_type({6, 0, 0}, sidb_technology::cell_type::NORMAL);
-    lyt.assign_cell_type({8, 0, 0}, sidb_technology::cell_type::NORMAL);
-
-    lyt.assign_cell_type({12, 0, 0}, sidb_technology::cell_type::NORMAL);
-    lyt.assign_cell_type({14, 0, 0}, sidb_technology::cell_type::NORMAL);
-
-    lyt.assign_cell_type({18, 0, 0}, sidb_technology::cell_type::OUTPUT);
-    lyt.assign_cell_type({20, 0, 0}, sidb_technology::cell_type::OUTPUT);
-
-    // output perturber
-    lyt.assign_cell_type({24, 0, 0}, sidb_technology::cell_type::NORMAL);
-
-    const sidb_100_cell_clk_lyt_siqad lat{lyt};
-
-    sidb_simulation_parameters sim_params{};
-
-    sim_params.base = 2;
-
-    const is_operational_params params{sim_params};
-
-    CHECK(is_operational(lyt, std::vector<tt>{create_id_tt()}, params).first == operational_status::OPERATIONAL);
-}
+#endif
diff --git a/test/algorithms/simulation/sidb/quickexact.cpp b/test/algorithms/simulation/sidb/quickexact.cpp
@@ -1355,6 +1355,8 @@ TEMPLATE_TEST_CASE("QuickExact simulation of a Y-shaped SiDB OR gate with input
     }
 }
 
+// to save runtime in the CI, this test is only run in RELEASE mode
+#ifdef NDEBUG
 TEMPLATE_TEST_CASE("QuickExact simulation of a Y-shaped SiDB OR gate with input 01", "[quickexact], [quality]",
                    sidb_100_cell_clk_lyt_siqad, cds_sidb_100_cell_clk_lyt_siqad)
 {
@@ -2091,3 +2093,4 @@ TEMPLATE_TEST_CASE("QuickExact AND gate simulation of Si-111 surface", "[quickex
         CHECK(ground_state.front().get_charge_state({23, 29, 1}) == sidb_charge_state::NEGATIVE);
     }
 }
+#endif