✨ SAT-based clock number assignment #381
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…ayout` while disregarding the underlying clocking scheme
… scheme (clock number assignment) for a given unclocked gate-level layout
…signment of crossing tiles' clock zones
… starting clock of 1 instead of 0
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include/fiction/algorithms/physical_design/determine_clocking.hpp
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include/fiction/algorithms/physical_design/determine_clocking.hpp
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Drewniok
reviewed
Feb 14, 2024
Drewniok
reviewed
Feb 14, 2024
include/fiction/algorithms/physical_design/determine_clocking.hpp
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simon1hofmann
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Feb 14, 2024
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Thanks a lot for the addition @marcelwa.
Looks really good 👍
…efault SAT solver because of its slight performance advantage
…efault SAT solver because of its slight performance advantage
Drewniok
approved these changes
Feb 14, 2024
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Description
This PR introduces a new SAT-based algorithm that can determine valid clock number assignments to gate-level layouts. It ignores the present clocking information of the given layout and only looks at the gate-wire connections present in the layout. Based on these connections, it creates a SAT instance that formulates the clock number assignment problem. This algorithm is exact; that is, if a valid clock number assignment exists, it will eventually be found. Vice versa, if no clock number assignment can be found, none exists. In the former case, the algorithm will override the clocking information present in the layout via the assignment of an irregular clock map.
Checklist: