A simple monocycle cpu based on mips instruction set, which served as a part of course 'computer organization and design'. Monocycle cpu is indicated as all instructions will be completed in one clock cycle, which means the CPI(cycle per instruction) of monocycle cpu is 1. So, the cycle of monocycle cpu is so long that we seldom use monocycle cpu in practice. However, to know exactly the datapath of mono cpu is the key of understanding and realizing multicycle cpu and pipeline cpu in my view.
Develop environment: Xilinx_Vivado_SDK_2014.2_0606_1_Win64 FPGA:xc7a100tcsg324-1
File struct: directory ./source |adder.v -- adder module whose top module is alu |alu.v -- alu , achieve basic arithmetic fuction |alu_controller.v -- alu control , used to translate op to control signal in alu whose top module is alu |barrel_shift_mips.v -- barrel_shifter , used to logic right/left shift , round right shift , arithmetic right shift |controller.v -- control signal generator , used to translate instruction to significent signal in cpu |extend_selector.v -- extend immediate instruction according extend signal generated by controller |momo_cpu.v --top module |program_counter.v -- pc |register_mips32.v -- 32 registers in mips cpu , register0 is always zero |selector21_5.v -- 2 to 1 selector with data path wedth 5 bits |selector21_32.v -- 2 to 1 selector with data path width 32 bits directory ./simulate |test_alu_controller.v --simulate alu controller |test_barrel_shift_mips.v --simulate barrel shifter |test_controller.v --simulate controller |test_program_counter.v --simulate pc |test_register_mips32.v --simulate register group
How to use? open vivado and creat a project, then add the source file and simulate file into the project. The file struct and logic relationship between each module are self-organized.