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Latest register set + generated RDL outputs + integ spec updates. Doe…
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…s not compile.
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@calebofearth
calebofearth committed Nov 16, 2024
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32 changes: 23 additions & 9 deletions docs/CaliptraIntegrationSpecification.md
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Original file line number Diff line number Diff line change
Expand Up @@ -63,8 +63,7 @@ The following table describes integration parameters.
| **Defines** | **Defines file** | **Description** |
| :--------- | :--------- | :--------- |
| CALIPTRA_INTERNAL_TRNG | config_defines.svh | Defining this enables the internal TRNG source. |
| CALIPTRA_INTERNAL_UART | config_defines.svh | Defining this enables the internal UART. |
| CALIPTRA_INTERNAL_QSPI | config_defines.svh | Defining this enables the internal QSPI. |
| CALIPTRA_MODE_SUBSYSTEM | config_defines.svh | Defining this enables Caliptra to operate in subsystem mode. This includes features such as the debug unlock flow, AXI DMA (for recovery flow), subsystem level straps, among other capabilites. See [FIXME](FIXME) for more details |
| USER_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that is used in [clk_gate.sv](../src/libs/rtl/clk_gate.sv). USER_ICG replaces the clock gating module, CALIPTRA_ICG, defined in [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_ICG. |
| TECH_SPECIFIC_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the USER_ICG macro) to be used in place of the native Caliptra clock gate module. |
| USER_EC_RV_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that is used in the RISC-V core. USER_EC_RV_ICG replaces the clock gating module, TEC_RV_ICG, defined in [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_EC_RV_ICG. |
Expand Down Expand Up @@ -150,12 +149,26 @@ The following tables describe the interface signals.
| jtag_trst_n | 1 | input | Asynchronous assertion<br>Synchronous deassertion to jtag_tck | |
| jtag_tdo | 1 | output | Synchronous to jtag_tck | |

*Table 10: UART interface*

| Signal name | Width | Driver | Synchronous (as viewed from Caliptra’s boundary) | Description |
| :--------- | :--------- | :--------- | :--------- | :--------- |
| uart_tx | 1 | output | | UART transmit pin |
| uart_rx | 1 | input | | UART receive pin |
*Table 10: Subsystem Straps and Control*

| Signal name | Width | Driver | Synchronous (as viewed from Caliptra’s boundary) | Description |
| :---------- | :--------- | :--------- | :----------------------------------------------- | :--------- |
| strap_ss_soc_ifc_base_addr | 64 | Input Strap | Synchronous to clk | |
| strap_ss_mci_base_addr | 64 | Input Strap | Synchronous to clk | |
| strap_ss_recovery_ifc_base_addr | 64 | Input Strap | Synchronous to clk | |
| strap_ss_otp_fc_base_addr | 64 | Input Strap | Synchronous to clk | |
| strap_ss_uds_seed_base_addr | 64 | Input Strap | Synchronous to clk | |
| strap_ss_prod_debug_unlock_auth_pk_hash_reg_bank_offset | 32 | Input Strap | Synchronous to clk | |
| strap_ss_num_of_prod_debug_unlock_auth_pk_hashes | 32 | Input Strap | Synchronous to clk | |
| strap_ss_strap_rsvd_0 | 32 | Input Strap | Synchronous to clk | |
| strap_ss_strap_rsvd_1 | 32 | Input Strap | Synchronous to clk | |
| strap_ss_strap_rsvd_2 | 32 | Input Strap | Synchronous to clk | |
| strap_ss_strap_rsvd_3 | 32 | Input Strap | Synchronous to clk | |
| ss_debug_intent | 1 | Input Strap | Synchronous to clk | |
| ss_dbg_manuf_enable | 1 | Output | Synchronous to clk | |
| ss_dbg_prod_enable | 1 | Output | Synchronous to clk | |
| ss_soc_dbg_unlock_level | 32 | Output | Synchronous to clk | |
| ss_generic_fw_exec_ctrl | 64 | Output | Synchronous to clk | |

*Table 11: Security and miscellaneous*

Expand Down Expand Up @@ -227,6 +240,7 @@ Caliptra firmware internally has the capability to force release the mailbox bas
### Straps

Straps are signal inputs to Caliptra that are sampled once on reset exit, and the latched value persists throughout the remaining uptime of the system. Straps are sampled on either caliptra pwrgood signal deassertion or cptra\_noncore\_rst\_b deassertion – refer to interface table for list of straps.
In 2.0, Caliptra adds support for numerous Subsystem-level straps. These straps are initialized on reset exit to the value from the external port, but may also be rewritten by the SoC firmware at any time prior to CPTRA_FUSE_WR_DONE being set.

### Obfuscation key

Expand Down Expand Up @@ -505,7 +519,7 @@ The following memories are exported:
* Instruction Closely-Coupled Memory (ICCM)
* Data Closely Coupled Memory (DCCM)

Table 4 indicates the signals contained in the memory interface. Direction is relative to the exported memory wrapper that is instantiated outside of the Caliptra subsystem (that is, from the testbench perspective).
Table 8 indicates the signals contained in the memory interface. Direction is relative to the exported memory wrapper that is instantiated outside of the Caliptra subsystem (that is, from the testbench perspective).

## SRAM timing behavior
* [Writes] Input wren signal is asserted simultaneously with input data and address. Input data is stored at the input address 1 clock cycle later.
Expand Down
74 changes: 20 additions & 54 deletions src/integration/rtl/caliptra_reg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -5650,12 +5650,8 @@
#define SOC_IFC_REG_CPTRA_HW_CONFIG (0xe0)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (0x1)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_LOW (1)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK (0x2)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_LOW (2)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (0x4)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK (0x8)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_RSVD_EN_LOW (1)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_RSVD_EN_MASK (0xe)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (0x10)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5)
Expand Down Expand Up @@ -5720,6 +5716,10 @@
#define SOC_IFC_REG_CPTRA_HW_CAPABILITIES (0x128)
#define CLP_SOC_IFC_REG_CPTRA_FW_CAPABILITIES (0x3003012c)
#define SOC_IFC_REG_CPTRA_FW_CAPABILITIES (0x12c)
#define CLP_SOC_IFC_REG_CPTRA_CAP_LOCK (0x30030130)
#define SOC_IFC_REG_CPTRA_CAP_LOCK (0x130)
#define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 (0x30030140)
#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 (0x140)
#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 (0x30030144)
Expand Down Expand Up @@ -5748,10 +5748,6 @@
#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK (0x170)
#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_DEBUG_AUTH_PK_HASH_REG_BANK_OFFSET (0x30030174)
#define SOC_IFC_REG_CPTRA_DEBUG_AUTH_PK_HASH_REG_BANK_OFFSET (0x174)
#define CLP_SOC_IFC_REG_CPTRA_NUM_OF_DEBUG_AUTH_PK_HASHES (0x30030178)
#define SOC_IFC_REG_CPTRA_NUM_OF_DEBUG_AUTH_PK_HASHES (0x178)
#define CLP_SOC_IFC_REG_FUSE_UDS_SEED_0 (0x30030200)
#define SOC_IFC_REG_FUSE_UDS_SEED_0 (0x200)
#define CLP_SOC_IFC_REG_FUSE_UDS_SEED_1 (0x30030204)
Expand Down Expand Up @@ -5916,14 +5912,6 @@
#define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (0x354)
#define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x30030358)
#define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x358)
#define CLP_SOC_IFC_REG_FUSE_PROD_DBG_UNLOCK_TOKEN_0 (0x3003035c)
#define SOC_IFC_REG_FUSE_PROD_DBG_UNLOCK_TOKEN_0 (0x35c)
#define CLP_SOC_IFC_REG_FUSE_PROD_DBG_UNLOCK_TOKEN_1 (0x30030360)
#define SOC_IFC_REG_FUSE_PROD_DBG_UNLOCK_TOKEN_1 (0x360)
#define CLP_SOC_IFC_REG_FUSE_PROD_DBG_UNLOCK_TOKEN_2 (0x30030364)
#define SOC_IFC_REG_FUSE_PROD_DBG_UNLOCK_TOKEN_2 (0x364)
#define CLP_SOC_IFC_REG_FUSE_PROD_DBG_UNLOCK_TOKEN_3 (0x30030368)
#define SOC_IFC_REG_FUSE_PROD_DBG_UNLOCK_TOKEN_3 (0x368)
#define CLP_SOC_IFC_REG_SS_SOC_IFC_BASE_ADDR_L (0x30030500)
#define SOC_IFC_REG_SS_SOC_IFC_BASE_ADDR_L (0x500)
#define CLP_SOC_IFC_REG_SS_SOC_IFC_BASE_ADDR_H (0x30030504)
Expand All @@ -5944,40 +5932,12 @@
#define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L (0x520)
#define CLP_SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H (0x30030524)
#define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H (0x524)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_0 (0x30030560)
#define SOC_IFC_REG_SS_SOC_NONCE_0 (0x560)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_1 (0x30030564)
#define SOC_IFC_REG_SS_SOC_NONCE_1 (0x564)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_2 (0x30030568)
#define SOC_IFC_REG_SS_SOC_NONCE_2 (0x568)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_3 (0x3003056c)
#define SOC_IFC_REG_SS_SOC_NONCE_3 (0x56c)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_4 (0x30030570)
#define SOC_IFC_REG_SS_SOC_NONCE_4 (0x570)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_5 (0x30030574)
#define SOC_IFC_REG_SS_SOC_NONCE_5 (0x574)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_6 (0x30030578)
#define SOC_IFC_REG_SS_SOC_NONCE_6 (0x578)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_7 (0x3003057c)
#define SOC_IFC_REG_SS_SOC_NONCE_7 (0x57c)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_8 (0x30030580)
#define SOC_IFC_REG_SS_SOC_NONCE_8 (0x580)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_9 (0x30030584)
#define SOC_IFC_REG_SS_SOC_NONCE_9 (0x584)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_10 (0x30030588)
#define SOC_IFC_REG_SS_SOC_NONCE_10 (0x588)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_11 (0x3003058c)
#define SOC_IFC_REG_SS_SOC_NONCE_11 (0x58c)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_12 (0x30030590)
#define SOC_IFC_REG_SS_SOC_NONCE_12 (0x590)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_13 (0x30030594)
#define SOC_IFC_REG_SS_SOC_NONCE_13 (0x594)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_14 (0x30030598)
#define SOC_IFC_REG_SS_SOC_NONCE_14 (0x598)
#define CLP_SOC_IFC_REG_SS_SOC_NONCE_15 (0x3003059c)
#define SOC_IFC_REG_SS_SOC_NONCE_15 (0x59c)
#define CLP_SOC_IFC_REG_SS_DEBUG_INTENT (0x300305a0)
#define SOC_IFC_REG_SS_DEBUG_INTENT (0x5a0)
#define CLP_SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (0x30030528)
#define SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (0x528)
#define CLP_SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (0x3003052c)
#define SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (0x52c)
#define CLP_SOC_IFC_REG_SS_DEBUG_INTENT (0x30030530)
#define SOC_IFC_REG_SS_DEBUG_INTENT (0x530)
#define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0)
#define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (0x1)
#define CLP_SOC_IFC_REG_SS_STRAP_RSVD_0 (0x300305c0)
Expand Down Expand Up @@ -6016,8 +5976,14 @@
#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_MASK (0x80)
#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_LOW (8)
#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (0x100)
#define CLP_SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL (0x300305e8)
#define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL (0x5e8)
#define CLP_SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (0x300305e8)
#define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (0x5e8)
#define CLP_SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (0x300305ec)
#define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (0x5ec)
#define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 (0x300305f0)
#define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 (0x5f0)
#define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 (0x300305f4)
#define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 (0x5f4)
#define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_0 (0x30030600)
#define SOC_IFC_REG_INTERNAL_OBF_KEY_0 (0x600)
#define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_1 (0x30030604)
Expand Down
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