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Fix PC setup after waking from clock gating in Verilator
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Internal-tag: [#53905]
Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>
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robertszczepanski committed Jan 18, 2024
1 parent 886805b commit b59a04e
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Showing 5 changed files with 46 additions and 48 deletions.
2 changes: 1 addition & 1 deletion .github/workflows/build-test-verilator.yml
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Expand Up @@ -123,7 +123,7 @@ jobs:
outputs:
test_names: ${{ steps.output-matrix.outputs.test_names }}
env:
EXCLUDE_TESTS: "smoke_test_clk_gating, smoke_test_cg_wdt, smoke_test_mbox_cg, smoke_test_kv_cg, smoke_test_doe_cg"
EXCLUDE_TESTS: "smoke_test_clk_gating"
steps:
- uses: actions/checkout@v3
- name: Install deps
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6 changes: 3 additions & 3 deletions src/integration/stimulus/L0_regression.yml
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Expand Up @@ -9,7 +9,7 @@ contents:
#add back for aes
#- ../test_suites/smoke_test_aes/smoke_test_aes.yml
- ../test_suites/smoke_test_mbox/smoke_test_mbox.yml
#- ../test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.yml
- ../test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.yml
- ../test_suites/smoke_test_sha512/smoke_test_sha512.yml
- ../test_suites/smoke_test_sha256/smoke_test_sha256.yml
- ../test_suites/smoke_test_sha_accel/smoke_test_sha_accel.yml
Expand Down Expand Up @@ -37,7 +37,7 @@ contents:
- ../test_suites/smoke_test_kv_hmac_flow/smoke_test_kv_hmac_flow.yml
- ../test_suites/smoke_test_kv_sha512_flow/smoke_test_kv_sha512_flow.yml
- ../test_suites/smoke_test_kv_crypto_flow/smoke_test_kv_crypto_flow.yml
#- ../test_suites/smoke_test_kv_cg/smoke_test_kv_cg.yml
- ../test_suites/smoke_test_kv_cg/smoke_test_kv_cg.yml
- ../test_suites/pv_hash_and_sign/pv_hash_and_sign.yml
- ../test_suites/smoke_test_pcr_signing/smoke_test_pcr_signing.yml
- ../test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml
Expand All @@ -47,7 +47,7 @@ contents:
- ../test_suites/smoke_test_doe_rand/smoke_test_doe_rand.yml
- ../test_suites/smoke_test_doe_scan/smoke_test_doe_scan.yml
- ../test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.yml
#- ../test_suites/smoke_test_doe_cg/smoke_test_doe_cg.yml
- ../test_suites/smoke_test_doe_cg/smoke_test_doe_cg.yml
# data vault tests
- ../test_suites/smoke_test_datavault_basic/smoke_test_datavault_basic.yml
- ../test_suites/smoke_test_datavault_reset/smoke_test_datavault_reset.yml
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6 changes: 0 additions & 6 deletions src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
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Expand Up @@ -761,16 +761,10 @@ module `TEC_RV_ICG

assign enable = EN | SE;

`ifdef VERILATOR
always @(negedge CK) begin
en_ff <= enable;
end
`else
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
`endif
assign Q = CK & en_ff;

endmodule
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78 changes: 41 additions & 37 deletions tools/scripts/Makefile
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Expand Up @@ -119,43 +119,47 @@ $(eval TBFILES = $(shell cat $(TBDIR)/../config/caliptra_top_tb.vf | grep -v '+i
#defines += $(RV_ROOT)/design/include/el2_def.sv
#defines += $(BUILD_DIR)/el2_pdef.vh
includes = -I$(BUILD_DIR)
#
# .--------------------------------------------------------------------------------.
# | Verilator does not support unpacked structs/unions - waive this warning so |
# | that unpacked structs are treated as packed. This should only impact files |
# | generated from RDL register files, which use unpacked structs liberally. |
# '-----------------------------------------------------------------------------+--'
# |
# .---------------------------------------------------------------------. |
# | This is flagged for every generated SystemVerilog file defining a | |
# | register block. The field_storage signal is the target of the | |
# | warning, indicating multiple drivers/different clocking. | |
# '----------------------------------------------------------------+----' |
# | |
# .------------------------------------------------------. | |
# | PeakRDL implements the default incrsaturate behavior | | |
# | for counter registers by performing a > comparison | | |
# | with an all-ones value (i.e. cnt > 32'hFFFFFFFF) | | |
# | which, by definition, can never be true. Verilator | | |
# | warns that this will compile to a constant 0. | | |
# '------------------------------------------------+-----' | |
# | | |
# .--------------------------------------------. | | |
# | Vectors that are little bit-endian are not | | | |
# | supported by Verilator, according to a | | | |
# | warning that is thrown. This is supposedly | | | |
# | resolved as of version 3.720, according | | | |
# | to the release notes. | | | |
# '-----------------------------------+--------' | | |
# | | | |
# .------------------------------. | | | |
# | Inherited from ChipsAlliance | | | | |
# | VeeR repository provided | | | | |
# | Makefile | | | | |
# '-----+------------+-----------' | | | |
# | | | | | |
# v v v v v v
suppress = -Wno-WIDTH -Wno-UNOPTFLAT -Wno-LITENDIAN -Wno-CMPCONST -Wno-MULTIDRIVEN -Wno-UNPACKED
# .----------------------------------------------------------------------------------------------.
# | Verilator is optimized for edge-sensitive (flop-based) designs. However, it supports latches |
# | with most performance optimizations disabled and warns that it may be non-intentional latch. |
# '-------------------------------------------------------------------------------------------+--'
# |
# .--------------------------------------------------------------------------------. |
# | Verilator does not support unpacked structs/unions - waive this warning so | |
# | that unpacked structs are treated as packed. This should only impact files | |
# | generated from RDL register files, which use unpacked structs liberally. | |
# '-----------------------------------------------------------------------------+--' |
# | |
# .---------------------------------------------------------------------. | |
# | This is flagged for every generated SystemVerilog file defining a | | |
# | register block. The field_storage signal is the target of the | | |
# | warning, indicating multiple drivers/different clocking. | | |
# '----------------------------------------------------------------+----' | |
# | | |
# .------------------------------------------------------. | | |
# | PeakRDL implements the default incrsaturate behavior | | | |
# | for counter registers by performing a > comparison | | | |
# | with an all-ones value (i.e. cnt > 32'hFFFFFFFF) | | | |
# | which, by definition, can never be true. Verilator | | | |
# | warns that this will compile to a constant 0. | | | |
# '------------------------------------------------+-----' | | |
# | | | |
# .--------------------------------------------. | | | |
# | Vectors that are little bit-endian are not | | | | |
# | supported by Verilator, according to a | | | | |
# | warning that is thrown. This is supposedly | | | | |
# | resolved as of version 3.720, according | | | | |
# | to the release notes. | | | | |
# '-----------------------------------+--------' | | | |
# | | | | |
# .------------------------------. | | | | |
# | Inherited from ChipsAlliance | | | | | |
# | VeeR repository provided | | | | | |
# | Makefile | | | | | |
# '-----+------------+-----------' | | | | |
# | | | | | | |
# v v v v v v v
suppress = -Wno-WIDTH -Wno-UNOPTFLAT -Wno-LITENDIAN -Wno-CMPCONST -Wno-MULTIDRIVEN -Wno-UNPACKED -Wno-LATCH

# CFLAGS for verilator generated Makefiles. Without -std=c++17 it
# complains for `auto` variables
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2 changes: 1 addition & 1 deletion tools/scripts/run_verilator_l0_regression.py
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Expand Up @@ -123,7 +123,7 @@ def getTestNames():
# Skip clk gating tests in Verilator until PC issue is resolved
# https://github.com/chipsalliance/Cores-VeeR-EL2/issues/88
# https://github.com/chipsalliance/caliptra-rtl/issues/126
if (re.search(r'(smoke_test_clk_gating|smoke_test_cg_wdt)',x.groups()[0])) :
if (re.search(r'(smoke_test_clk_gating)',x.groups()[0])) :
continue
integrationTestSuiteList.append(x.groups()[0])

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