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Update ABR submodule
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@calebofearth
calebofearth committed Nov 4, 2024
1 parent 4745c92 commit cba07a4
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion submodules/adams-bridge
Submodule adams-bridge updated 49 files
+1 −1 .github/workflow_metadata/pr_hash
+1 −1 .github/workflow_metadata/pr_timestamp
+26 −0 config/compilespecs.yml
+55 −2 src/abr_libs/config/compile.yml
+40 −20 src/decompose/rtl/decompose.sv
+9 −3 src/decompose/rtl/decompose_ctrl.sv
+0 −1 src/makehint/config/compile.yml
+0 −1 src/makehint/config/makehint.vf
+1 −2 src/makehint/config/makehint_tb.vf
+19 −11 src/makehint/rtl/makehint.sv
+0 −130 src/makehint/rtl/makehint_sample_buffer.sv
+1 −2 src/mldsa_top/config/mldsa_top.vf
+1 −2 src/mldsa_top/config/mldsa_top_tb.vf
+71 −0 src/mldsa_top/rtl/kv_def.rdl
+5 −3 src/mldsa_top/rtl/mldsa_config_defines.svh
+113 −7 src/mldsa_top/rtl/mldsa_ctrl.sv
+6 −4 src/mldsa_top/rtl/mldsa_reg.rdl
+200 −35 src/mldsa_top/rtl/mldsa_reg.sv
+60 −0 src/mldsa_top/rtl/mldsa_reg_pkg.sv
+98 −1 src/mldsa_top/rtl/mldsa_reg_uvm.sv
+41 −9 src/mldsa_top/rtl/mldsa_top.sv
+2 −2 src/mldsa_top/stimulus/testsuites/mldsa_top_nightly_random_regression.yml
+12 −3 src/mldsa_top/stimulus/uvmf_mldsa_top_promote_regression.yml
+ − src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium5
+ − src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium5.exe
+ − src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium5_debug.exe
+1 −2 src/mldsa_top/uvmf/config/uvmf_mldsa.vf
+ − src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/test_dilithium5
+ − ..._top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/test_dilithium5_debug
+58 −25 src/norm_check/rtl/norm_check_ctrl.sv
+1 −1 src/norm_check/rtl/norm_check_defines_pkg.sv
+25 −8 src/norm_check/rtl/norm_check_top.sv
+363 −115 src/norm_check/tb/norm_check_tb.sv
+23 −2 src/ntt_top/Model/maksed_gadgets.py
+31 −0 src/ntt_top/Model/testForMasking.py
+1 −0 src/ntt_top/config/compile.yml
+42 −0 src/ntt_top/config/ntt_mult_reduction_tb.vf
+334 −72 src/ntt_top/rtl/ntt_ctrl.sv
+114 −0 src/ntt_top/rtl/ntt_shuffle_buffer.sv
+103 −32 src/ntt_top/rtl/ntt_top.sv
+1 −1 src/ntt_top/stimulus/testsuites/ntt_nightly_directed_regression.yml
+76 −12 src/ntt_top/tb/ntt_top_tb.sv
+5 −1 src/ntt_top/tb/ntt_wrapper.sv
+6 −6 src/ntt_top/utb/interfaces/mem_if.sv
+5 −5 src/ntt_top/utb/mem_agent/mem_txn.sv
+3 −1 src/ntt_top/utb/ntt_agent/ntt_txn.sv
+10 −6 src/ntt_top/utb/ntt_utb_top/ntt_utb_top.sv
+11 −11 src/ntt_top/utb/scoreboard/ntt_sb.sv
+2 −0 tools/scripts/reg_gen.py

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