fixup! Add type ascription to implicits from instantiable (#3615)

src/test/scala/chiselTests/util/SparseVecSpec.scala

@@ -22,7 +22,7 @@ class SparseVecTest(addrWidth: Int) extends BasicTester {
   val mapping = Seq(
     0 -> a,
     1 -> b,
-    15 -> c
+    2 -> c
   )
 
   val size = BigInt(2).pow(addrWidth).toInt
@@ -45,8 +45,10 @@ class SparseVecTest(addrWidth: Int) extends BasicTester {
 
   sparseVecs.foreach {
     case (name, vec) =>
+      printf(s"$name:\n")
       (0 until size).foreach {
         case i =>
+          printf(s"  $i: %x =? %x\n", vec(i.U), reference(i.U))
           assert(vec(i.U) === reference(i.U), s"failed index $i")
       }
   }
@@ -55,8 +57,35 @@ class SparseVecTest(addrWidth: Int) extends BasicTester {
 
 }
 
+class Old extends RawModule {
+  val addr = IO(Input(UInt(1.W)))
+  val a = IO(Input(Vec(1, Bool())))
+  val b = IO(Output(Bool()))
+
+  b := a(addr)
+}
+
+class New extends RawModule {
+  val addr = IO(Input(UInt(1.W)))
+  val a = IO(Input(Vec(1, Bool())))
+  val b = IO(Output(Bool()))
+
+  private val vec = SparseVec.onehot(
+    2,
+    Seq(
+      0 -> a(0)
+    )
+  )
+
+  b := vec(addr)
+}
+
 class SparseVecSpec extends ChiselFlatSpec with Utils {
   "SparseVec" should "work" in {
     assertTesterPasses(new SparseVecTest(4))
   }
+  it should "be exactly equivalent to a dynamic index" in {
+    ChiselStage.emitSystemVerilog(new Old) should include("assign b = a_0")
+    ChiselStage.emitSystemVerilog(new New) should include("assign b = a_0")
+  }
 }