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Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (
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#2031)

PR #2023 fixed a composition issue for chisel3 biconnects delegating to
FIRRTL partial connect when compatibility mode Bundles are elements of
chisel3 Bundles. It missed an important case though that caused
previously working code to break.

The bug is fixed by doing the automatic flipping for compatibility mode
Bundles that have "Input" as a direction in addition to those that are
"Flipped".
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jackkoenig authored Jul 9, 2021
1 parent 4b7b771 commit 5183ef8
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Showing 2 changed files with 10 additions and 4 deletions.
3 changes: 2 additions & 1 deletion core/src/main/scala/chisel3/internal/BiConnect.scala
Original file line number Diff line number Diff line change
Expand Up @@ -120,9 +120,10 @@ private[chisel3] object BiConnect {
if (notStrict) {
// chisel3 <> is commutative but FIRRTL <- is not
val flipped = {
import ActualDirection._
// Everything is flipped when it's the port of a child
val childPort = left_r._parent.get != context_mod
val isFlipped = left_r.direction == ActualDirection.Bidirectional(ActualDirection.Flipped)
val isFlipped = Seq(Bidirectional(Flipped), Input).contains(left_r.direction)
isFlipped ^ childPort
}
val (newLeft, newRight) = if (flipped) pair.swap else pair
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Original file line number Diff line number Diff line change
Expand Up @@ -294,16 +294,21 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
compile {
object Compat {
import Chisel._
class Foo extends Bundle {
class BiDir extends Bundle {
val a = Input(UInt(8.W))
val b = Output(UInt(8.W))
}
class Struct extends Bundle {
val a = UInt(8.W)
}
}
import chisel3._
import Compat._
class Bar extends Bundle {
val foo1 = new Foo
val foo2 = Flipped(new Foo)
val bidir1 = new BiDir
val bidir2 = Flipped(new BiDir)
val struct1 = Output(new Struct)
val struct2 = Input(new Struct)
}
// Check every connection both ways to see that chisel3 <>'s commutativity holds
class Child extends RawModule {
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