minimal bug reproduce

src/test/scala/chiselTests/ProbeSpec.scala

@@ -731,4 +731,30 @@ class ProbeSpec extends ChiselFlatSpec with MatchesAndOmits with Utils {
       "output b : Probe<UInt<2>, LayerA.LayerB>"
     )()
   }
+
+
+  "FixedIO" should "work" in {
+    class Baz extends Bundle {
+      val ele = Bool()
+    }
+    class FooIO extends Bundle with IgnoreSeqInBundle {
+      val probeA = Output(Vec(2, Probe(new Baz)))
+    }
+    @chisel3.experimental.hierarchy.instantiable
+    class Foo extends FixedIORawModule(new FooIO) {
+      val bars = Seq.fill(2)(chisel3.experimental.hierarchy.Instantiate(new Bar))
+      bars.zipWithIndex.foreach { case (bar, idx) =>
+         define(io.probeA(idx), bar.io.probeA)
+      }
+    }
+    class BarIO extends Bundle with IgnoreSeqInBundle {
+      val probeA = Output(Probe(new Baz))
+    }
+    @chisel3.experimental.hierarchy.instantiable
+    class Bar extends FixedIORawModule(new BarIO) {
+      val bazWire = 0.U.asTypeOf(new Baz)
+      define(io.probeA, ProbeValue(bazWire))
+    }
+    ChiselStage.emitSystemVerilog(new Foo)
+  }
 }