Recursively generate one-hot multiplexers for Aggregates

chipsalliance · Aug 17, 2020 · 9f26d89 · 9f26d89
1 parent 387d870
commit 9f26d89
Showing 1 changed file with 7 additions and 3 deletions.
diff --git a/core/src/main/scala/chisel3/SeqUtils.scala b/core/src/main/scala/chisel3/SeqUtils.scala
@@ -113,10 +113,14 @@ private[chisel3] object SeqUtils {
             buildAndOrMultiplexor(sels.zip(inWidthMatched))
           }
 
-        case _: Aggregate =>
+        case agg: Aggregate =>
           val allDefineWidth = in.forall { case (_, element) => element.widthOption.isDefined }
-          if(allDefineWidth) {
-            buildAndOrMultiplexor(in)
+          if (allDefineWidth) {
+            val out = Wire(agg)
+            out.getElements.zipWithIndex.map { case (element, i) =>
+              element := oneHotMux(in.map(_._1) zip in.map(_._2.asInstanceOf[Aggregate].getElements(i)))
+            }
+            out.asInstanceOf[T]
           }
           else {
             throwException(s"Cannot Mux1H with aggregates with inferred widths")