Patch fix #1109 (#1346)

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
chipsalliance · Feb 19, 2020 · aac6e17 · aac6e17
1 parent d183168
commit aac6e17
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/chiselFrontend/src/main/scala/chisel3/RawModule.scala b/chiselFrontend/src/main/scala/chisel3/RawModule.scala
@@ -49,8 +49,10 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
               " name is already taken by another port!")
           }
           port.setRef(ModuleIO(this, _namespace.name(name)))
-        case None => Builder.error(s"Unable to name port $port in $this, " +
-          "try making it a public field of the Module")
+        case None =>
+          Builder.error(s"Unable to name port $port in $this, " +
+            "try making it a public field of the Module")
+          port.setRef(ModuleIO(this, "<UNNAMED>"))
       }
     }
   }