Why do modulus(%) and compare(===/<=/>=) operators combinations lead to firrtl.FirrtlInternalException?

[Wolf-Tungsten]

I have a module in which a modulus operator % is combined with a compare operators such as ===/<=/>=.

When I tried to generate Verilog code for this module, I got a firrtl.FirrtlInternalException.

Here is a trivial module can reproduce this issue:

package modulus

import chisel3._

class Modulus extends Module {
    val io = IO(new Bundle{
        val in1 = Input(SInt(8.W))
        val in2 = Input(SInt(8.W))
        val out = Output(Bool())
    })
    io.out := ((io.in1 % io.in2) === 0.S)
} 

object Modulus extends App {
    val verilogString = (new chisel3.stage.ChiselStage).emitVerilog(new Modulus, Array.concat(args, Array("-td=./verilog-output")))
}

[info] running modulus.Modulus 
Elaborating design...
Done elaborating.
[error] (run-main-11) firrtl.FirrtlInternalException: Internal Error! Unexpected non-SInt type for Reference(_io_out_T,UIntType(IntWidth(8)),NodeKind,SourceFlow) in DoPrim(eq,ArrayBuffer(Reference(_io_out_T,UIntType(IntWidth(8)),NodeKind,SourceFlow), SIntLiteral(0,IntWidth(8))),ArrayBuffer(),UnknownType)
[error] Please file an issue at https://github.com/ucb-bar/firrtl/issues
[error] firrtl.FirrtlInternalException: Internal Error! Unexpected non-SInt type for Reference(_io_out_T,UIntType(IntWidth(8)),NodeKind,SourceFlow) in DoPrim(eq,ArrayBuffer(Reference(_io_out_T,UIntType(IntWidth(8)),NodeKind,SourceFlow), SIntLiteral(0,IntWidth(8))),ArrayBuffer(),UnknownType)
[error] Please file an issue at https://github.com/ucb-bar/firrtl/issues
[error]         at firrtl.Utils$.error(Utils.scala:491)
[error]         at firrtl.Utils$.throwInternalError(Utils.scala:164)
[error]         at firrtl.VerilogEmitter.castIf$1(VerilogEmitter.scala:279)
[error]         at firrtl.VerilogEmitter.op_stream(VerilogEmitter.scala:324)
[error]         at firrtl.VerilogEmitter.emitCol(VerilogEmitter.scala:165)
[error]         at firrtl.VerilogEmitter.$anonfun$emitCol$2(VerilogEmitter.scala:204)
[error]         at firrtl.VerilogEmitter.$anonfun$emitCol$2$adapted(VerilogEmitter.scala:203)
[error]         at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error]         at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error]         at scala.collection.immutable.List.foldLeft(List.scala:91)
………………

[sequencer]

opps.
This should be a bug for SInt.

[jackkoenig]

I've created an issue from this discussion, it is definitely a bug: #2012

[sequencer]

I'm marking this as answered, and move future discussion to #2012.
Thanks @Wolf-Tungsten to report this.