Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Chisel stage #1004

Merged
merged 15 commits into from
Jun 3, 2019
Merged

Chisel stage #1004

merged 15 commits into from
Jun 3, 2019

Conversation

seldridge
Copy link
Member

@seldridge seldridge commented Jan 25, 2019

Related issue:

Type of change: other enhancement

Impact: API addition (no impact on existing code)

Development Phase: implementation

This PR provides a reimplementation of the Chisel Driver as a Stage. This involves three major additions/modifications:

  1. Addition of a chisel3.stage package that implements ChiselStage
  2. Addition of tests for chisel3.stage
  3. Modification of chisel3.Driver to use ChiselStage with a compatibility layer

For a more exhaustive introduction to Stage/Phase, see chipsalliance/firrtl#1005.

Todo

  • Add Scaladoc
  • Deprecate ChiselExecutionResultView
    • This is an implicit object and can't be deprecated. Instead it's now private [chisel3]
  • Note in documentation what is compatibility layer
  • Mutate options to match old behavior

Structure

This PR

  1. Add expected annotations
  2. Write the CLI
  3. Add the xOptions class (which is not a case class)
  4. Write an options view to construct your xOptions
  5. Add methods to existing ExecutionOptions to reconstruct an AnnotationSeq
  6. Write all new phases to reimplement Driver functionality:
    • chisel3.stage.phases.Checks
    • chisel3.stage.phases.Elaborate
    • chisel3.stage.phases.Convert
    • chisel3.stage.phases.Emitter
    • chisel3.stage.phases.AddImplicitOutputFile
    • chisel3.stage.phases.AddImplicitOutputAnnotationFile
  7. Write ChiselStage
  8. Write any necessary compatibility layer and/or re-use existing compatibility layers
  9. Write the new Stage
  10. Replace old Driver logic with new phases

Anecdotally, this process is non-linear. I did this by incrementally porting the old Driver in pieces and moving whatever functionality I could into it when I had it. Git's --squash and --fixup help a lot for keeping the history sane when you do rebase. Additionally, writing tests as you go is tedious, but likely necessary.

Most of the porting difficulty is (1) deciding, without constraints, what you want the new stage to do and (2) writing the compatibility layer that interfaces this with the old Driver.

There are several temptations here that I think should be avoided:

  • Opting to have the old Driver call an old, already ported, sub-Driver (e.g., have chisel3.Driver call firrtl.Driver). This causes the old Driver and the new Stage to use different code paths. While not insurmountable, this would seem to introduce the potential for subtle bugs between the two versions.
  • For the same reasons as above, no functionality should differ between the old Driver and the new stage excepting compatibility layer phases and a view to an execution result.

Most of difficulty in not yielding to these temptations is dealing with situations where the old Driver does not do things in a linear, pipe-like order. E.g., the old Chisel Driver would do elaboration and then continually refer back to the elaborated Chisel circuit. The stage doesn't need to do this as it's moving directly towards a CHIRRTL circuit or to run the FIRRTL compiler. However, the compatibility wrapper has to reconstruct what happened. This PR gets around this, kludgily, by viewing deleted annotations. This isn't really advised, but for a compatibility layer it's passable.

Depends on:

Includes:

Release Notes

  • Adds ChiselStage, a the Chisel Driver as a firrtl.options.Stage
  • The original Chisel Driver is converted to a compatibility layer around ChiselStage

@seldridge seldridge requested a review from a team as a code owner January 25, 2019 22:42
@seldridge seldridge force-pushed the chisel-stage branch 2 times, most recently from a3d2f19 to 83e17a0 Compare January 30, 2019 17:24
@seldridge seldridge added the Merge with merge commit Please merge with a merge commit, do not squash and merg label Jan 31, 2019
@seldridge seldridge force-pushed the chisel-stage branch 4 times, most recently from 6888507 to 0cfb04d Compare February 1, 2019 08:24
@azidar azidar mentioned this pull request Feb 6, 2019
@seldridge seldridge added this to the 3.2.0 milestone Apr 21, 2019
@seldridge seldridge force-pushed the chisel-stage branch 2 times, most recently from 5d169ae to 2d6df13 Compare April 23, 2019 03:37
@seldridge seldridge mentioned this pull request Apr 23, 2019
@seldridge seldridge force-pushed the chisel-stage branch 2 times, most recently from ce0b2da to 9aa76dd Compare April 26, 2019 20:35
@seldridge
Copy link
Member Author

Note: this is causing testers to fail on:

  • chisel3.iotesters.BlackBoxVerilogDeliverySpec
  • examples.AccumulatorBlackBoxPeekPokeTestVerilator

@chick
Copy link
Contributor

chick commented Apr 29, 2019

I am out today but will try and dig into this tonight

@chick
Copy link
Contributor

chick commented Apr 30, 2019

This looks like a test set-up error. It is failing because VCS is not present. I'll ask @ucbjrl about it this morning

@seldridge
Copy link
Member Author

Looking at this. There's an annoyance in that the old Driver.execute mutates the options and passes that to FIRRTL. This has the effect that running Driver.execute and then inspecting the options manager will differ with this PR as it stands (e.g., getAnnotations). I'm seeing about a fix to preserver backwards compatibility.

@seldridge seldridge force-pushed the chisel-stage branch 2 times, most recently from c769e1b to 6a1c44c Compare May 3, 2019 17:04
@seldridge
Copy link
Member Author

Following up on the previous comment: the specific issue stems from Driver.scala#L236. Inside chisel3.Driver.execute the input options manager is mutated and passed to firrtl.Driver.execute. FIRRTL does not (as far as I can tell) mutate the options manager. However, anything downstream that looks at the mutated options manager has a view of the options just before FIRRTL runs. This includes all input FIRRTL annotations which may be necessary for things like testers.

This is fixed by adding a couple of additional phases. In the new chisel3.Driver, a NoRunFirrtlAnnotation is added to disable ChiselStage running FirrtlStage. After ChiselStage a MutateOptionsManager(a: ExecutionOptionsManager with ...) runs to mutate the options manager. FirrtlStage is then possibly re-enabled. Then a new MaybeFirrtlStage runs that will run FirrtlStage if it's supposed to.

Corollary: mutable state is the root of all evil.

Addendum: if a Stage isn't working, it probably needs more Phases....

Copy link
Contributor

@chick chick left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think this looks very good. Tests seem clean
Lot's of nitty gritty details
Some errors and warnings in scaladoc
a few other scala style

src/main/scala/chisel3/stage/ChiselStage.scala Outdated Show resolved Hide resolved
src/main/scala/chisel3/stage/package.scala Outdated Show resolved Hide resolved
src/main/scala/chisel3/stage/phases/Convert.scala Outdated Show resolved Hide resolved
src/main/scala/chisel3/stage/phases/Emitter.scala Outdated Show resolved Hide resolved
src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala Outdated Show resolved Hide resolved
src/test/scala/chiselTests/stage/phases/ConvertSpec.scala Outdated Show resolved Hide resolved
Copy link
Contributor

@chick chick left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Looks good to me. All my nits are cleaned up.
@jackkoenig @ducky64 either of you want to weigh in here too?


def toAnnotations: AnnotationSeq =
(if (!runFirrtlCompiler) { Seq(NoRunFirrtlCompilerAnnotation) } else { Seq() }) ++
(if (printFullStackTrace) { Some(PrintFullStackTraceAnnotation) } else { None })
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I didn't realize you can ++ Option but it makes sense, cool!

seldridge and others added 15 commits May 22, 2019 16:17
This adds the following FIRRTL Annotations to Chisel:

- NoRunFirrtlCompilerAnnotation
- PrintFullStackTraceAnnotation
- ChiselGeneratorAnnotation
- ChiselCircuitAnnotation
- ChiselOutputFileAnnotation

This includes tests for ChiselGeneratorAnnotation as this Annotation
is able to be constructed from a String and to elaborate itself.

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
This adds an Elaborate Phase that expands ChiselGeneratorAnnotations
into ChiselCircuitAnnotations and deletes the original.

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
This coalesces three distinct operations into one Convert Phase:

  1. Chisel Circuit to FIRRTL Circuit (CHIRRTL) conversion
  2. Conversion of Chisel Annotations to FIRRTL Annotations
  3. Generation of RunFirrtlTransformAnnotations

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
This adds an Emitter Phase that writes a ChiselCircuitAnnotation to
a file if a ChiselOutputFileAnnotation is present.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
This adds ChiselStage, a reimplementation of chisel3.Driver as a
firrtl.options.Stage. This is simplistically described as a pipeline
of Phases.

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
This includes phases necessary to provide backwards compatibility with
the old Chisel3 Driver. These are placed in a DriverCompatibility
object inside chisel3.stage.phases. The following four phases are
included:
  - AddImplicitOutputFile (from a TopNameAnnotation)
  - AddImplicitOutputAnnotationFile phase
  - DisableFirrtlStage (to disable ChiselStage running FirrtlStage)
  - MutateOptionsManager (to update options after ChiselStage)
  - ReEnableFirrtlStage (to renable FirrtlStage if needed)

Additionally, this adds a view of a ChiselExecutionResult for
providing the legacy return type of the Chisel Driver.

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Adds a method to enable conversion from ChiselExecutionOptions back to
an AnnotationSeq.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
This converts the original chisel3.Driver to use
chisel3.stage.ChiselStage. This is implemented in the following way:

  1. ExecutionOptions are converted to an AnnotationSeq

  2. The AnnotationSeq is preprocessed using phases contained in the
     Chisel DriverCompatibility objects. One of these *disables* the
     execution of FirrtlStage by ChiselStage.
  3. ChiselStage runs on the preprocessed AnnotationSeq
  4. The input ExecutionOptionsManager is mutated based on the output
     of ChiselStage.
  5. The FIRRTL stage is re-enabled if it's supposed to run and
     selected FIRRTL DriverCompatibility phases run.
  6. FirrtlStage runs
  7. The output AnnotationSeq is "viewed" as a ChiselExecutionResult

This modifies the original DriverSpec to make it more verbose with the
addition of info statements. The functionality of the DriverSpec is
unmodified.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
@chick chick merged commit 821fe17 into master Jun 3, 2019
@seldridge seldridge deleted the chisel-stage branch June 4, 2019 12:56
jackkoenig pushed a commit that referenced this pull request Feb 28, 2023
Add "mverilog" Compiler Option, MinimumVerilogEmitter
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Merge with merge commit Please merge with a merge commit, do not squash and merg
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants