Don't use MuxLookup default for full mapping

[seldridge]

If you use MuxLookup with a full mapping, i.e., you fully enumerate all possible values for a key, you still wind up with unused hardware being generated in the case of a Mux failure case that is never used and which FIRRTL does not optimize away.

This PR modifies MuxLookup to examine if the user has provided a full mapping and to not emit the additional failure case for the initial Mux. In effect, the default is immediately discarded and the first mapping becomes the default.

This generally improves Verilog generation for users that are using MuxLookup like a Verilog case statement.

This would benefit from tests, but there weren't any tests already written. 😭 I can write them (read: I have not fully tested this). I just figured I would drop the PR first.

Example

For the following Chisel:

import chisel3._
import chisel3.util.MuxLookup
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}

class Qux extends RawModule {
  val in = IO(Input(Vec(2, UInt(2.W))))
  val sel = IO(Input(UInt(1.W)))
  val out = IO(Output(UInt(2.W)))

  val mapping = Seq( 0.U -> in(0),
                     1.U -> in(1) )

  out := MuxLookup(sel, DontCare, mapping)
}

(new ChiselStage).execute(Array("-X", "verilog"), Seq(ChiselGeneratorAnnotation(() => new Qux)))

Without this PR:

module Qux(
  input  [1:0] in_0,
  input  [1:0] in_1,
  input        sel,
  output [1:0] out
);
  wire [1:0] _T_1; // @[Mux.scala 68:16]
  wire  _T_3; // @[Mux.scala 68:19]
  assign _T_1 = sel ? in_1 : 2'h0; // @[Mux.scala 68:16]
  assign _T_3 = 1'h0 == sel; // @[Mux.scala 68:19]
  assign out = _T_3 ? in_0 : _T_1; // @[<pastie> 29:7]
endmodule

With this PR:

module Qux(
  input  [1:0] in_0,
  input  [1:0] in_1,
  input        sel,
  output [1:0] out
);
  assign out = sel ? in_1 : in_0; // @[<console> 23:7]
endmodule

Related issue:

Type of change: other enhancement

Impact: API modification (in terms of generating different Verilog)

Development Phase: implementation

Release Notes

• Improved MuxLookup code generation

[albert-magyar]

@jackkoenig I would review this, but I wrote some of the code, so you should take a look. The literal exhaustiveness check handles the bitwidth corner case oddities, too.

[jackkoenig]

1 question/concern, otherwise, LGTM!

[jackkoenig]

LGTM!