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Use innermost builder cause to trim stack trace #1380

Merged
merged 1 commit into from
Mar 21, 2020
Merged

Use innermost builder cause to trim stack trace #1380

merged 1 commit into from
Mar 21, 2020

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seldridge
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Change the logic for determining which nested ChiselException cause to
use for a trimmed stack trace. Previously, this would use the
outermost. This commit changes this to use the innermost.

Related issue: chipsalliance/rocket-chip#2340 (review)

For the example @jackkoenig is showing, with this PR cherry-picked onto 3.2.x you get:

[error] java.lang.IllegalArgumentException: requirement failed: hello world
[error] 	...
[error] 	at freechips.rocketchip.rocket.DCacheModule.<init>(DCache.scala:96)
[error] 	at freechips.rocketchip.rocket.DCache.module$lzycompute(DCache.scala:84)
[error] 	at freechips.rocketchip.rocket.DCache.module(DCache.scala:84)
[error] ocketchiat freechips.rocketchip.rocket.DCache.module(DCache.scala:83)
[error] 	at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$2(LazyModule.scala:158)
[error] 	at chisel3.Module$.do_apply(Module.scala:52)
[error] 	at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:158)
[error] 	at scala.collection.immutable.List.flatMap(List.scala:338)
[error] 	at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:156)
[error] 	at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:155)
[error] 	at freechips.rocketchip.diplomacy.LazyModuleImp.instantiate(LazyModule.scala:185)
[error] 	at freechips.rocketchip.diplomacy.LazyModuleImp.<init>(LazyModule.scala:186)
[error] 	at freechips.rocketchip.tile.BaseTileModuleImp.<init>(BaseTile.scala:246)
[error] 	at freechips.rocketchip.tile.RocketTileModuleImp.<init>(RocketTile.scala:120)
[error] 	at freechips.rocketchip.tile.RocketTile.module$lzycompute(RocketTile.scala:103)
[error] 	at freechips.rocketchip.tile.RocketTile.module(RocketTile.scala:103)
[error] 	at freechips.rocketchip.tile.RocketTile.module(RocketTile.scala:33)
[error] 	at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$2(LazyModule.scala:158)
[error] 	at chisel3.Module$.do_apply(Module.scala:52)
[error] 	at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:158)
[error] 	at scala.collection.immutable.List.flatMap(List.scala:338)
[error] 	at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:156)
[error] 	at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:155)
[error] 	at freechips.rocketchip.diplomacy.LazyModuleImp.instantiate(LazyModule.scala:185)
[error] 	at freechips.rocketchip.diplomacy.LazyModuleImp.<init>(LazyModule.scala:186)
[error] 	at freechips.rocketchip.subsystem.BareSubsystemModuleImp.<init>(BaseSubsystem.scala:34)
[error] 	at freechips.rocketchip.subsystem.BaseSubsystemModuleImp.<init>(BaseSubsystem.scala:129)
[error] 	at freechips.rocketchip.subsystem.RocketSubsystemModuleImp.<init>(RocketSubsystem.scala:80)
[error] 	at freechips.rocketchip.system.ExampleRocketSystemModuleImp.<init>(ExampleRocketSystem.scala:24)
[error] 	at freechips.rocketchip.system.ExampleRocketSystem.module$lzycompute(ExampleRocketSystem.scala:21)
[error] 	at freechips.rocketchip.system.ExampleRocketSystem.module(ExampleRocketSystem.scala:21)
[error] 	at freechips.rocketchip.system.TestHarness.$anonfun$dut$1(TestHarness.scala:17)
[error] 	at chisel3.Module$.do_apply(Module.scala:52)
[error] 	at freechips.rocketchip.system.TestHarness.<init>(TestHarness.scala:17)
[error] 	at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
[error] 	at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
[error] 	at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
[error] 	at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
[error] 	at freechips.rocketchip.stage.phases.PreElaboration.$anonfun$transform$1(PreElaboration.scala:31)
[error] 	... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace)

Type of change: bug report

Impact: no functional change

Development Phase: implementation

Release Notes

  • Improve stack trace trimming for nested stages

@seldridge
Use innermost builder cause to trim stack trace
75c4bce 
Change the logic for determining which nested ChiselException cause to
use for a trimmed stack trace. Previously, this would use the
outermost. This commit changes this to use the innermost.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
@seldridge seldridge added the Bugfix Fixes a bug, will be included in release notes label Mar 21, 2020
@seldridge seldridge added this to the 3.2.X milestone Mar 21, 2020
@seldridge seldridge requested a review from a team as a code owner March 21, 2020 00:55
@jackkoenig
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I can confirm this fixes the issue I noted in chipsalliance/rocket-chip#2340 (review)

@jackkoenig jackkoenig added the Please Merge Accepted PRs that are ready to be merged. Useful when waiting on CI. label Mar 21, 2020
@mergify mergify bot merged commit 5d269ce into master Mar 21, 2020
mergify bot pushed a commit that referenced this pull request Mar 21, 2020
@seldridge
Use innermost builder cause to trim stack trace (#1380)
2acf2b6 
Change the logic for determining which nested ChiselException cause to
use for a trimmed stack trace. Previously, this would use the
outermost. This commit changes this to use the innermost.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 5d269ce)
@mergify mergify bot mentioned this pull request Mar 21, 2020
Merged
@mergify mergify bot added the Backported This PR has been backported label Mar 21, 2020
mergify bot added a commit that referenced this pull request Mar 21, 2020
@mergify @seldridge
Use innermost builder cause to trim stack trace (#1380) (#1381)
7a9ae29 
Change the logic for determining which nested ChiselException cause to
use for a trimmed stack trace. Previously, this would use the
outermost. This commit changes this to use the innermost.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 5d269ce)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
@jackkoenig jackkoenig deleted the ChiselException-likelyCause-innermost branch July 7, 2021 03:44
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