Enable Cat of Zero Element Vec (bp #1623)

core/src/main/scala/chisel3/SeqUtils.scala

@@ -15,12 +15,15 @@ private[chisel3] object SeqUtils {
     * in the sequence forms the most significant bits.
     *
     * Equivalent to r(n-1) ## ... ## r(1) ## r(0).
+    * @note This returns a `0.U` if applied to a zero-element `Vec`.
     */
   def asUInt[T <: Bits](in: Seq[T]): UInt = macro SourceInfoTransform.inArg
 
   /** @group SourceInfoTransformMacros */
   def do_asUInt[T <: Bits](in: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = {
-    if (in.tail.isEmpty) {
+    if (in.isEmpty) {
+      0.U
+    } else if (in.tail.isEmpty) {
       in.head.asUInt
     } else {
       val left = prefix("left") {

src/main/scala/chisel3/util/Cat.scala

@@ -25,6 +25,7 @@ object Cat {
     * in the sequence forms the least significant bits.
     *
     * Equivalent to r(0) ## r(1) ## ... ## r(n-1).
+    * @note This returns a `0.U` if applied to a zero-element `Vec`.
     */
   def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse)
 }

src/test/scala/chiselTests/util/CatSpec.scala

@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util
+
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util.Cat
+
+import chiselTests.ChiselFlatSpec
+
+object CatSpec {
+
+  class JackIsATypeSystemGod extends MultiIOModule {
+    val in  = IO(Input (Vec(0, UInt(8.W))))
+    val out = IO(Output(UInt(8.W)))
+
+    out := Cat(in)
+  }
+
+}
+
+class CatSpec extends ChiselFlatSpec {
+
+  import CatSpec._
+
+  behavior of "util.Cat"
+
+  it should "not fail to elaborate a zero-element Vec" in {
+
+    ChiselStage.elaborate(new JackIsATypeSystemGod)
+
+  }
+
+}