[stevo]: allow bitwidth inference on output of shift register #355
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superseded by #370 |
mwachs5
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Dec 29, 2022
Bumps [chisel3](https://github.com/freechipsproject/chisel3) from `9b8536b` to `80b3b28`. - [Release notes](https://github.com/freechipsproject/chisel3/releases) - [Commits](9b8536b...80b3b28) --- updated-dependencies: - dependency-name: chisel3 dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com> Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
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Chisel couldn't find bitwidth when I tried to use
Reverse(ShiftRegister(value, 2))
because Reverse calls getWidth. This fixes that issue. See #354 for the old fix attempt, where I changed RegNext instead of ShiftRegister