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[stevo]: shift register enable signal now enables ALL registers in th… #370

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merged 3 commits into from
Nov 18, 2016
Merged

[stevo]: shift register enable signal now enables ALL registers in th… #370

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669a0da
[stevo]: shift register enable signal now enables ALL registers in th…
stevobailey Nov 17, 2016
8889abf
[stevo]: remove n=1 case
stevobailey Nov 18, 2016
edf92aa
Merge branch 'master' into sr_enable_fix
stevobailey Nov 18, 2016
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6 changes: 2 additions & 4 deletions src/main/scala/chisel3/util/Reg.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -55,10 +55,8 @@ object ShiftRegister
*/
def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = {
// The order of tests reflects the expected use cases.
if (n == 1) {
RegEnable(in, en)
} else if (n != 0) {
RegNext(apply(in, n-1, en))
if (n != 0) {
RegEnable(apply(in, n-1, en), en)
} else {
in
}
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