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Remove unnecessary overrides of lref and ref in Property (backport #4309) #4310

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Jul 25, 2024
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26 changes: 2 additions & 24 deletions core/src/main/scala/chisel3/properties/Property.scala
Original file line number Diff line number Diff line change
Expand Up @@ -264,6 +264,8 @@ sealed trait Property[T] extends Element { self =>

override def typeName: String = s"Property[${tpe.getPropertyType().serialize}]"

override def toString: String = stringAccessor("Property")

/** Bind this node to the in-memory graph.
*/
private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection): Unit = {
Expand Down Expand Up @@ -297,30 +299,6 @@ sealed trait Property[T] extends Element { self =>
tpe.getPropertyType()
}

/** Internal API: returns a ref that can be assigned to, if consistent with the binding.
*/
private[chisel3] override def lref(implicit info: SourceInfo): ir.Node = {
requireIsHardware(this)
requireVisible()
topBindingOpt match {
case Some(binding: ReadOnlyBinding) =>
throwException(s"internal error: attempted to generate LHS ref to ReadOnlyBinding $binding")
case Some(binding: TopBinding) => ir.Node(this)
case opt => throwException(s"internal error: unknown binding $opt in generating LHS ref")
}
}

/** Internal API: returns a ref, if bound.
*/
private[chisel3] override def ref: ir.Arg = {
requireIsHardware(this)
requireVisible()
topBindingOpt match {
case Some(binding: TopBinding) => ir.Node(this)
case opt => throwException(s"internal error: unknown binding $opt in generating RHS ref")
}
}

/** Perform addition as defined by FIRRTL spec section Integer Add Operation.
*/
final def +(that: Property[T])(implicit ev: PropertyArithmeticOps[Property[T]], sourceInfo: SourceInfo): Property[T] =
Expand Down
18 changes: 18 additions & 0 deletions src/test/scala/chiselTests/experimental/DataView.scala
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@ import chisel3.experimental.{Analog, HWTuple2}
import chisel3.experimental.BundleLiterals._
import chisel3.experimental.VecLiterals._
import chisel3.probe._
import chisel3.properties.Property
import chisel3.reflect.DataMirror.internal.chiselTypeClone
import chisel3.util.{Decoupled, DecoupledIO, Valid, ValidIO}
import chiselTests.ChiselFlatSpec
Expand Down Expand Up @@ -1212,6 +1213,23 @@ class DataViewSpec extends ChiselFlatSpec {
ChiselStage.emitCHIRRTL(new MyModule)
}

it should "support view of Properties in a List[Property]" in {
class MyBundle extends Bundle {
val prop = Property[String]()
}
class ChildModule extends RawModule {
val io = IO(Output(new MyBundle))
}
class MyModule extends Module {
val out = IO(Output(Property[List[String]]()))
val child = Module(new ChildModule)
val view = child.io.viewAs[MyBundle]
out := Property(List(view.prop))
}
val chirrtl = ChiselStage.emitCHIRRTL(new MyModule)
chirrtl should include("propassign out, List<String>(child.io.prop)")
}

behavior.of("PartialDataView")

it should "still error if the mapping is non-total in the view" in {
Expand Down
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