Added API to get Verilog from Chisel #676
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This mostly looks good.
Also, does it make sense for this to be more general? Verilog is very much just one FIRRTL backend (though probably the most useful, for now), so this specific functionality seems like something that might be in utils or something rather than core.
src/main/scala/chisel3/Driver.scala
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| @@ -95,6 +95,20 @@ object Driver extends BackendCompilationUtilities { | |||
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| def emit[T <: RawModule](ir: Circuit): String = Emitter.emit(ir) | |||
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| def emitVerilog[T <: RawModule](gen: () => T): String = { | |||
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Why are two signatures needed? And can you just make one call the other (so we can be a little more DRY)?
src/main/scala/chisel3/Driver.scala
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| } | ||
| } | ||
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| def emitVerilog[T <: RawModule](gen: => T): String = { |
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Do we want scaladocs here?
edwardcwang
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| * @return the resulting String containing the design in Verilog | ||
| */ | ||
| def emitVerilog[T <: RawModule](gen: => T): String = { | ||
| execute(Array[String](), { () => gen }) match { |
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Do we ever care about wanting to pass arguments to emitVerilog? (e.g. optional argument)
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Seems like an options manager or an array of string should be passed in. overloaded definitions for each one
| def emitVerilog[T <: RawModule](gen: => T): String = { | ||
| execute(Array[String](), { () => gen }) match { | ||
| case ChiselExecutionSuccess(_, _, Some(firrtl.FirrtlExecutionSuccess(_, verilog))) => verilog | ||
| case _ => sys.error("Cannot get Verilog!") |
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Does it make sense to use ChiselException so that this can be caught?
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