Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add Module.currentModule for getting a reference to the current Module #810

Merged
merged 1 commit into from
Apr 22, 2018
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 2 additions & 0 deletions chiselFrontend/src/main/scala/chisel3/core/Module.scala
Original file line number Diff line number Diff line change
Expand Up @@ -75,6 +75,8 @@ object Module {
def clock: Clock = Builder.forcedClock
/** Returns the implicit Reset */
def reset: Reset = Builder.forcedReset
/** Returns the current Module */
def currentModule: Option[BaseModule] = Builder.currentModule
}

/** Abstract base class for Modules, an instantiable organizational unit for RTL.
Expand Down
52 changes: 28 additions & 24 deletions src/test/scala/chiselTests/Module.scala
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
package chiselTests

import chisel3._
import chisel3.experimental.{withClock, withReset}

class SimpleIO extends Bundle {
val in = Input(UInt(32.W))
Expand All @@ -26,37 +27,13 @@ class ModuleVec(val n: Int) extends Module {
}
}

/*
class ModuleVecTester(c: ModuleVec) extends Tester(c) {
for (t <- 0 until 16) {
val test_ins = Array.fill(c.n){ rnd.nextInt(256) }
for (i <- 0 until c.n)
poke(c.io.ins(i), test_ins(i))
step(1)
for (i <- 0 until c.n)
expect(c.io.outs(i), test_ins(i) + 1)
}
}
*/

class ModuleWire extends Module {
val io = IO(new SimpleIO)
val inc = Wire(chiselTypeOf(Module(new PlusOne).io))
inc.in := io.in
io.out := inc.out
}

/*
class ModuleWireTester(c: ModuleWire) extends Tester(c) {
for (t <- 0 until 16) {
val test_in = rnd.nextInt(256)
poke(c.io.in, test_in)
step(1)
expect(c.io.out, test_in + 1)
}
}
*/

class ModuleWhen extends Module {
val io = IO(new Bundle {
val s = new SimpleIO
Expand Down Expand Up @@ -122,4 +99,31 @@ class ModuleSpec extends ChiselPropSpec {
elaborate { new ModuleRewrap }
}).getMessage should include("This is probably due to rewrapping a Module instance")
}

property("object Module.clock should return a reference to the currently in scope clock") {
elaborate(new Module {
val io = IO(new Bundle {
val clock2 = Input(Clock())
})
assert(Module.clock eq this.clock)
withClock(io.clock2) { assert(Module.clock eq io.clock2) }
})
}
property("object Module.reset should return a reference to the currently in scope reset") {
elaborate(new Module {
val io = IO(new Bundle {
val reset2 = Input(Bool())
})
assert(Module.reset eq this.reset)
withReset(io.reset2) { assert(Module.reset eq io.reset2) }
})
}
property("object Module.currentModule should return an Option reference to the current Module") {
def checkModule(mod: Module): Boolean = Module.currentModule.map(_ eq mod).getOrElse(false)
elaborate(new Module {
val io = IO(new Bundle { })
assert(Module.currentModule.get eq this)
assert(checkModule(this))
})
}
}