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Avoid procedural wire assignment in test resource #979

Merged
merged 1 commit into from
Jan 9, 2019
Merged

Avoid procedural wire assignment in test resource #979

merged 1 commit into from
Jan 9, 2019

Commits on Jan 9, 2019

  1. Avoid procedural wire assignment in test resource 

    Verilator 4.008 dropped the hammer on procedural wire assignment to
align with the IEEE standard (first I've heard of this, though). The
VerilogVendingMachine.v test resource will error in Verilator 4.008
with a PROCASSWIRE error if you try to compile it. This fixes that
example to only assign to a register.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
    @seldridge
    seldridge committed Jan 9, 2019
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