Add license header to top of all code files

tests/carry/carry.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `default_nettype none
 `include "cblock/cblock.sim.v"
 

tests/carry/cblock/cblock.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `default_nettype none
 
 (* whitebox *)

tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 /*
  * `input wire a` should be detected as a clock because it drives the flip
  * flop.

tests/clocks/dff_one_clock/dff_one_clock.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 /*
  * `input wire a` should be detected as a clock because it drives the flip
  * flop.

tests/clocks/dff_two_clocks/dff_two_clocks.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 module BLOCK(c1, c2, a, b, c, o1, o2);
 	input wire c1;
 	input wire c2;

tests/clocks/input_attr_clock/input_attr_clock.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 /*
  * `input wire a` should be detected as a clock because of the `(* CLOCK *)`
  * attribute.

tests/clocks/input_attr_not_clock/block.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 /*
  * `input wire a` should be detected as a clock because it drives the flip
  * flop. However, it has the attribute CLOCK set to 0 which should force it

tests/clocks/input_named_clk/input_named_clk.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 /*
  * `input wire clk` should be detected as a clock despite this being a black
  * box module.

tests/clocks/input_named_rdclk/input_named_rdclk.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 /*
  * `input wire rdclk` should be detected as a clock despite this being a black
  * box module.

tests/clocks/input_named_regex/block.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* whitebox *)
 module BLOCK(
     input  wire clk,

tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 /*
  * `input wire rdclk` and `input wire wrclk` should be detected as a clock
  * despite this being a black box module.

tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 /*
  * `output wire rdclk` and `output wire wrclk` should be detected as a clock
  * despite this being a black box module.

tests/clocks/output_attr_clock/output_attr_clock.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 /*
  * `output wire o` should be detected as a clock because of the `(* CLOCK *)`
  * attribute.

tests/clocks/output_named_clk/output_named_clk.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 /*
  * `output wire clk` should be detected as a clock despite this being a black
  * box module.

tests/clocks/output_named_rdclk/output_named_rdclk.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 /*
  * `output wire rdclk` should be detected as a clock despite this being a black
  * box module.

tests/dsp/dsp_combinational/dsp_combinational.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `ifndef DSP_COMB
 `define DSP_COMB
 (* whitebox *)

tests/dsp/dsp_in_registered/dsp_in_registered.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../../vtr/dff/dff.sim.v"
 `include "../dsp_combinational/dsp_combinational.sim.v"
 

tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../../vtr/dff/dff.sim.v"
 `include "../dsp_combinational/dsp_combinational.sim.v"
 

tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../../vtr/dff/dff.sim.v"
 `include "../dsp_combinational/dsp_combinational.sim.v"
 

tests/dsp/dsp_modes/dsp_modes.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../dsp_combinational/dsp_combinational.sim.v"
 `include "../dsp_inout_registered/dsp_inout_registered.sim.v"
 `include "../dsp_in_registered/dsp_in_registered.sim.v"

tests/dsp/dsp_out_registered/dsp_out_registered.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../../vtr/dff/dff.sim.v"
 `include "../dsp_combinational/dsp_combinational.sim.v"
 

tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../../vtr/dff/dff.sim.v"
 `include "../dsp_combinational/dsp_combinational.sim.v"
 

tests/internal_conn/child/child.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* blackbox *)
 module CHILD(
   input  wire I,

tests/internal_conn/parent.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "./child/child.sim.v"
 
 module PARENT (

tests/io/input/ipad.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* CLASS="input" *)
 module IPAD(inpad);
     output wire inpad;

tests/io/output/opad.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* CLASS="output" *)
 module OPAD(outpad);
     input  wire outpad;

tests/logicbox/logicbox.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* whitebox *)
 module LOGICBOX (I, O);
 	input wire I;

tests/modes/inv.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "./not/not.sim.v"
 
 (* MODES="PASSTHROUGH;INVERT" *)