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[minor][abi] Document type alias lowering #117

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[minor][abi] Document type alias lowering #117

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4 changes: 4 additions & 0 deletions abi.md
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Expand Up @@ -142,6 +142,10 @@ payload as the first field and a packed bit vector as a second field. The
padding for each payload is set to ensure all padded payloads have the same bit
width as required by Verilog packed unions.

Type aliases shall be lowered to Verilog `typedef`{.verilog} with their inner types
recursively following these rules. Type aliases will be dropped if inner types are
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I'm not sure we want to encode dropping in the ABI. This would imply, maybe incorrectly, that if they have any name it is a bug. Perhaps "changes to the structure of a type will result in changes to the name of a type". Width/type/reset inference is actually a situation where we probably want to mutate the type but preserve it's name or at least of that option.

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i'm also a little leery of putting anything into the ABI for this. Aren't these aliases basically hints, and nothing is to be relied upon at the ABI level?

Should we say "there is no reliable mapping from type aliases to the emitted verilog, they are treated as hints only"?

mutated, for example by the type inference.

# Versioning Scheme of this Document

This is the versioning scheme that applies to version 1.0.0 and later.
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