Update RightShiftTests.fir to avoid buggy Counter pattern

* See chipsalliance/chisel#1408
chipsalliance · Apr 14, 2020 · 5b39a7f · 5b39a7f
1 parent 0407a53
commit 5b39a7f
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/test/integration/RightShiftTester.fir b/test/integration/RightShiftTester.fir
@@ -37,8 +37,8 @@ circuit RightShiftTester :
     dut.clock <= clock
     dut.reset <= reset
     reg T_6 : UInt<2>, clock with : (reset => (reset, UInt<2>("h00")))
+    node T_8 = eq(T_6, UInt<2>("h03"))
     when UInt<1>("h01") :
-      node T_8 = eq(T_6, UInt<2>("h03"))
       node T_10 = and(UInt<1>("h00"), T_8)
       node T_13 = add(T_6, UInt<1>("h01"))
       node T_14 = tail(T_13, 1)