FIRRTL accepts invalid code

[jackkoenig]

Checklist

• Did you specify the current behavior?
• Did you specify the expected behavior?
• Did you provide a code example showing the problem?
• Did you describe your environment? NA
• Did you specify relevant external information? NA

What is the current behavior?

circuit MyModule : 
  module MyModule : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip en : UInt<1>, out : UInt<8>, wrap : UInt<1>}
    
    reg count : UInt<3>, clock with : (reset => (reset, UInt<3>("h00")))
    when io.en :
      node _T = eq(count, UInt<3>("h07"))
      node _T_1 = add(count, UInt<1>("h01"))
      node _T_2 = tail(_T_1, 1)
      count <= _T_2
      skip 
    node wrap = and(io.en, _T)
    io.out <= count
    io.wrap <= wrap 

Given the above, FIRRTL will generate Verilog just fine.

What is the expected behavior?

It should error, because node wrap = and(io.en, _T) refers to _T which is defined inside the when scope

Steps to Reproduce

Yes, this comes from chisel3.util.Counter (lol whoops):
https://scastie.scala-lang.org/dtewI9H4R8mfdKRgxekx3A