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NMI implementation #2711

Merged
merged 9 commits into from
Nov 13, 2020
Merged

NMI implementation #2711

merged 9 commits into from
Nov 13, 2020

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ernie-sifive
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Related issue:

Type of change: feature request

Impact: API addition (no impact on existing code)

Development Phase: implementation

Release Notes

  • New NMI inputs covering both resumable and unresumable NMI
  • NMI wired through and integrated into the CSR module's interrupt handling infrastructure
  • New CSRs for NMI created.
  • New mnret instruction created.
  • Object model items now reflects presence of NMI
  • Bus Error Unit local interrupt is now wired to cause RNMI and populate mncause with a unique exception code.

src/main/scala/subsystem/HasTiles.scala Outdated Show resolved Hide resolved
*/
trait HasTileNMISources extends InstantiatesTiles { this: BaseSubsystem =>
/** NMI input bundle */
/** Source of Non-maskable Interrupt (NMI) input bundle to each tile. */
val tileNMINode = BundleBridgeEphemeralNode[NMI]()
val tileNMIIONodes: Seq[BundleBridgeSource[NMI]] = {
Seq.fill(tiles.size) {
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I think we need to make some kind of NexusSourceNode that accepts any number of left-hand-side connections so that you don't need this reference to tiles.size here. The miepNode above is playing a similar trick. Anyways, fine as-is and I will look at handling all three of these similarly in a future PR.

reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv)
new_prv := PRV.M
}
}.elsewhen (delegate && nmie) {
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Why is nmie here?

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The draft RNMI spec says that exceptions that occur while an NMI handler is active are handled in M-mode and affect mepc, mcause, etc. So they are never delegated. The next case of this when/else is taken in that case.

src/main/scala/rocket/CSR.scala Outdated Show resolved Hide resolved
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Thanks, @ernie-sifive - I reviewed only the RocketCore/CSRFile changes, but they LGTM.

@ernie-sifive ernie-sifive merged commit 12da135 into master Nov 13, 2020
@ernie-sifive ernie-sifive deleted the rnmi-unmi branch November 13, 2020 15:47
ZenithalHourlyRate added a commit to OpenRigil/rocket-chip that referenced this pull request Apr 2, 2022
Rocket already implemented NMI in chipsalliance#2711,
however, riscv-opcodes currently does not have NMI
as it is a WIP (See riscv/riscv-opcodes#67)

To avoid generating Instructions.scala from a patched riscv-opcodes,
putting NMI related insts/CSRs into CustomInstructions is reasonable.
ZenithalHourlyRate added a commit to OpenRigil/rocket-chip that referenced this pull request Apr 17, 2022
Rocket already implemented NMI in chipsalliance#2711,
however, riscv-opcodes currently does not have NMI
as it is a WIP (See riscv/riscv-opcodes#67)

To avoid generating Instructions.scala from a patched riscv-opcodes,
putting NMI related insts/CSRs into CustomInstructions is reasonable.
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5 participants