Bump Chisel and Firrtl #770
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aswaterman
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May 30, 2017
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This is failing due to bad interoperability of Chisel bundles in chisel3 code, I'm looking into it. |
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It's caused by a Bundle with an implicit output (ie. unspecified) being used as the next in a RegEnable (which is chisel3._ code). Fortunately, it is fixed by chipsalliance/chisel#617 |
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A couple of bug fixes, 2 fairly large performance bugs fixed in Firrtl