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Fix BlackParrot synthesis in Synlig
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robertszczepanski committed Sep 28, 2023
1 parent 93d7199 commit 3533443
Showing 1 changed file with 18 additions and 1 deletion.
19 changes: 18 additions & 1 deletion tools/runners/SynligYosys.py
Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,25 @@ def prepare_run_cb(self, tmp_dir, params):
for d in params["defines"]:
f.write(f" -D{d}")

mem_path = None
for fn in params["files"]:
f.write(f" {fn}")
# Remove unsynthesizable memory modules
if not fn.endswith("bsg_mem_1rw_sync_mask_write_bit_synth.v") \
and not fn.endswith("bsg_mem_1rw_sync_mask_write_bit.v"):
f.write(f" {fn}")
else:
mem_path = fn.split("/")

# Replace removed modules with synthesizable memory
if mem_path != None:
mem_path = mem_path[:-2]
str_mem_path = "/"

for p in mem_path:
str_mem_path = os.path.join(str_mem_path, p)
str_mem_path += "/hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v"

f.write(f" {str_mem_path}")

f.write("\n")

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