Build(deps): Bump third_party/surelog from 5c96759 to 21f2bc5
#6029
Triggered via pull request
November 13, 2024 07:46
dependabot[bot]
Status
Success
Total duration
1h 19m 13s
Artifacts
49
main.yml
on: pull_request
Matrix: build-binaries
Build tools
10m 43s
Emit Workflow Info
0s
Style check
1m 31s
Verify README Correctness (Installation From Sources)
41m 38s
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 31s
Large Designs Tests
/
Ibex (F4PGA synthesis)
11m 31s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
34m 28s
Large Designs Tests
/
Opentitan (synthesis)
53m 14s
Large Designs Tests
/
VeeR-EH1 (synthesis)
5m 30s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
16m 26s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
41m 45s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) with PySynlig)
39m 51s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
6m 39s
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests
/
Generate AST diff
1m 44s
Parsing Tests
/
Summary Generation
1m 38s
Verify README Correctness (Download And Run Release)
0s
Annotations
4 warnings
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Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
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Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build
third_party/OpenROAD-flow-scripts/logs
third_party/OpenROAD-flow-scripts/reports
third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
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Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
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Artifacts
Produced during runtime
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binaries-asan
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292 MB |
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binaries-package
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23.1 MB |
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binaries-plugin
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41.6 MB |
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binaries-pysynlig
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652 MB |
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binaries-release
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41.8 MB |
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bp_e_bp_unicore_cfg.edif
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3.9 MB |
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bsg-logs
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5.57 MB |
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bsg-outputs
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1.72 MB |
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formal-verification-logs-simple
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18.6 MB |
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formal-verification-logs-sv2v
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62.7 MB |
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formal-verification-logs-yosys
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50 MB |
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lowrisc_ibex_top_artya7_surelog_0.1.bit
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105 KB |
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lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
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616 KB |
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opentitan-logs-full
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5.09 MB |
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opentitan-logs-quick
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1.52 MB |
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plots_binaries-asan
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149 KB |
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plots_binaries-package
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146 KB |
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plots_binaries-plugin
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142 KB |
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plots_binaries-pysynlig
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176 KB |
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plots_binaries-release
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144 KB |
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plots_blackparrot_synth_asic
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245 KB |
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plots_blackparrot_synth_xilinx
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104 KB |
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plots_blackparrot_synth_xilinx_python
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227 KB |
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plots_build_tools
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79.3 KB |
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plots_formal_verification_simple
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113 KB |
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plots_formal_verification_sv2v
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115 KB |
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plots_formal_verification_yosys
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96.4 KB |
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plots_ibex_synth
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45.9 KB |
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plots_ibex_synth_f4pga
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80.1 KB |
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plots_opentitan_9d82960888_synth
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191 KB |
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plots_opentitan_parse_report_full
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80.2 KB |
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plots_opentitan_parse_report_quick
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42.8 KB |
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plots_opentitan_synth
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282 KB |
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plots_tests_asan_read_systemverilog
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222 KB |
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plots_tests_asan_read_uhdm
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167 KB |
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plots_tests_plugin_read_systemverilog
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36 KB |
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plots_tests_plugin_read_uhdm
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33.2 KB |
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plots_tests_release_read_systemverilog
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35.9 KB |
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plots_tests_release_read_uhdm
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33 KB |
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plots_veer_synth
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36.2 KB |
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python_bp_e_bp_unicore_cfg.edif
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3.9 MB |
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results_parsing_tests_asan_read_systemverilog
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1.6 MB |
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results_parsing_tests_asan_read_uhdm
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1.81 MB |
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results_parsing_tests_plugin_read_systemverilog
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1.53 MB |
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results_parsing_tests_plugin_read_uhdm
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1.78 MB |
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results_parsing_tests_release_read_systemverilog
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1.49 MB |
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results_parsing_tests_release_read_uhdm
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1.73 MB |
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tools
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39.1 MB |
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top_artya7.bit
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121 KB |
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