Build(deps): Bump third_party/surelog from `5c96759` to `21f2bc5` #6029

Job	Run time
Build Synlig Release	20m 53s
Build tools	10m 43s
Build Plugin	19m 52s
Emit Workflow Info	0s
Build Synlig (ASAN)	21m 54s
Style check	1m 31s
Build Package	21m 25s
Build PySynlig	25m 42s
Verify README Correctness (Installation From Sources)	41m 38s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	34m 28s
Large Designs Tests / Ibex (Vivado synthesis)	6m 31s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 31s
Formal Verification Tests / simple	17m 9s
Formal Verification Tests / sv2v	17m 12s
Large Designs Tests / Opentitan parsing (full/top-down)	13m 11s
Formal Verification Tests / yosys	14m 43s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 39s
Large Designs Tests / Opentitan parsing (quick)	6m 11s
Large Designs Tests / Black Parrot (ASIC synthesis)	41m 45s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	16m 26s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	39m 51s
Large Designs Tests / Opentitan (synthesis)	53m 14s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 30s
Parsing Tests / Test read_systemverilog release	4m 55s
Parsing Tests / Test read_uhdm release	4m 37s
Parsing Tests / Test read_systemverilog plugin	4m 55s
Parsing Tests / Test read_uhdm plugin	4m 35s
Parsing Tests / Test read_systemverilog asan	35m 33s
Parsing Tests / Test read_uhdm asan	25m 53s
Parsing Tests / Summary Generation	1m 38s
Parsing Tests / Generate AST diff	1m 44s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	8h 51m 49s

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