fix black box

Signed-off-by: unlsycn <unlsycn@unlsycn.com>
chipsalliance · Dec 1, 2024 · 63aca34 · 63aca34
1 parent 2084e07
commit 63aca34
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Showing 2 changed files with 14 additions and 22 deletions.
diff --git a/rocketv/src/SRAM.scala b/rocketv/src/SRAM.scala
@@ -54,11 +54,7 @@ class SRAMBlackbox(parameter: CIRCTSRAMParameter)
 
   private val wLogic = Seq
     .tabulate(parameter.write)(idx =>
-      Seq(
-        s"reg [${log2Ceil(parameter.depth) - 1}:0] _R${idx}_addr;",
-        s"reg _R${idx}_en;"
-      ) ++
-        Seq(s"always @(posedge R${idx}_clk) begin // RW${idx}") ++
+      Seq(s"always @(posedge W${idx}_clk) begin // RW${idx}") ++
         (if (parameter.masked)
            Seq.tabulate(parameter.width / parameter.maskGranularity)(i =>
              s"if (W${idx}_en & W${idx}_wmask[${i}]) Memory[W${idx}_addr][${i * parameter.maskGranularity}+:${parameter.maskGranularity}] <= RW${idx}_wdata[${(i + 1) * parameter.maskGranularity - 1}:${i * parameter.maskGranularity}];"
@@ -72,16 +68,16 @@ class SRAMBlackbox(parameter: CIRCTSRAMParameter)
   private val rLogic = Seq
     .tabulate(parameter.read)(idx =>
       Seq(
-        s"reg [${log2Ceil(parameter.depth) - 1}:0] _R${idx}_en;",
-        s"reg _R${idx}_addr;"
+        s"reg [${log2Ceil(parameter.depth) - 1}:0] _R${idx}_addr;",
+        s"reg _R${idx}_en;"
       ) ++
         Seq(
           s"always @(posedge R${idx}_clk) begin // R${idx}",
           s"_R${idx}_raddr <= R${idx}_addr;",
-          s"_R${idx}_ren <= R${idx}_ren;",
+          s"_R${idx}_en <= R${idx}_en;",
           s"end // RW${idx}"
         ) ++
-        Some(s"R${idx}_data = _R${idx}_ren ? Memory[_R${idx}_raddr] : ${parameter.width}'bx;")
+        Some(s"assign R${idx}_data = _R${idx}_ren ? Memory[_R${idx}_raddr] : ${parameter.width}'bx;")
     )
     .flatten
 
@@ -95,7 +91,7 @@ class SRAMBlackbox(parameter: CIRCTSRAMParameter)
         Seq(s"always @(posedge RW${idx}_clk) begin // RW${idx}") ++
         Seq(
           s"_RW${idx}_raddr <= RW${idx}_addr;",
-          s"_RW${idx}_ren <= RW${idx}_ren;",
+          s"_RW${idx}_ren <= RW${idx}_en;",
           s"_RW${idx}_rmode <= RW${idx}_rmode;"
         ) ++
         (if (parameter.masked)
@@ -105,7 +101,7 @@ class SRAMBlackbox(parameter: CIRCTSRAMParameter)
          else
            Seq(s"if (RW${idx}) Memory[RW${idx}_addr] <= RW${idx}_data;")) ++
         Seq(s"end // RW${idx}") ++
-        Seq(s"RW${idx}_rdata = _RW${idx}_ren ? Memory[_RW${idx}_raddr] : ${parameter.width}'bx;")
+        Seq(s"assign RW${idx}_rdata = _RW${idx}_ren ? Memory[_RW${idx}_raddr] : ${parameter.width}'bx;")
     )
     .flatten
 

diff --git a/t1/src/SRAM.scala b/t1/src/SRAM.scala
@@ -54,11 +54,7 @@ class SRAMBlackbox(parameter: CIRCTSRAMParameter)
 
   private val wLogic = Seq
     .tabulate(parameter.write)(idx =>
-      Seq(
-        s"reg [${log2Ceil(parameter.depth) - 1}:0] _R${idx}_addr;",
-        s"reg _R${idx}_en;"
-      ) ++
-        Seq(s"always @(posedge R${idx}_clk) begin // RW${idx}") ++
+      Seq(s"always @(posedge W${idx}_clk) begin // RW${idx}") ++
         (if (parameter.masked)
            Seq.tabulate(parameter.width / parameter.maskGranularity)(i =>
              s"if (W${idx}_en & W${idx}_wmask[${i}]) Memory[W${idx}_addr][${i * parameter.maskGranularity}+:${parameter.maskGranularity}] <= RW${idx}_wdata[${(i + 1) * parameter.maskGranularity - 1}:${i * parameter.maskGranularity}];"
@@ -72,16 +68,16 @@ class SRAMBlackbox(parameter: CIRCTSRAMParameter)
   private val rLogic = Seq
     .tabulate(parameter.read)(idx =>
       Seq(
-        s"reg [${log2Ceil(parameter.depth) - 1}:0] _R${idx}_en;",
-        s"reg _R${idx}_addr;"
+        s"reg [${log2Ceil(parameter.depth) - 1}:0] _R${idx}_addr;",
+        s"reg _R${idx}_en;"
       ) ++
         Seq(
           s"always @(posedge R${idx}_clk) begin // R${idx}",
           s"_R${idx}_raddr <= R${idx}_addr;",
-          s"_R${idx}_ren <= R${idx}_ren;",
+          s"_R${idx}_en <= R${idx}_en;",
           s"end // RW${idx}"
         ) ++
-        Some(s"R${idx}_data = _R${idx}_ren ? Memory[_R${idx}_raddr] : ${parameter.width}'bx;")
+        Some(s"assign R${idx}_data = _R${idx}_ren ? Memory[_R${idx}_raddr] : ${parameter.width}'bx;")
     )
     .flatten
 
@@ -95,7 +91,7 @@ class SRAMBlackbox(parameter: CIRCTSRAMParameter)
         Seq(s"always @(posedge RW${idx}_clk) begin // RW${idx}") ++
         Seq(
           s"_RW${idx}_raddr <= RW${idx}_addr;",
-          s"_RW${idx}_ren <= RW${idx}_ren;",
+          s"_RW${idx}_ren <= RW${idx}_en;",
           s"_RW${idx}_rmode <= RW${idx}_rmode;"
         ) ++
         (if (parameter.masked)
@@ -105,7 +101,7 @@ class SRAMBlackbox(parameter: CIRCTSRAMParameter)
          else
            Seq(s"if (RW${idx}) Memory[RW${idx}_addr] <= RW${idx}_data;")) ++
         Seq(s"end // RW${idx}") ++
-        Seq(s"RW${idx}_rdata = _RW${idx}_ren ? Memory[_RW${idx}_raddr] : ${parameter.width}'bx;")
+        Seq(s"assign RW${idx}_rdata = _RW${idx}_ren ? Memory[_RW${idx}_raddr] : ${parameter.width}'bx;")
     )
     .flatten