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[X86,SimplifyCFG] Support hoisting load/store with conditional faulti…
…ng (Part I) (llvm#96878) This is simplifycfg part of llvm#95515 In this PR, we support hoisting load/store with conditional faulting in `SimplifyCFGOpt::speculativelyExecuteBB` to eliminate conditional branches. This is for cases like ``` void test (int a, int *b) { if (a) *b = a; } ``` In the following patches, we will support the hoist in `SimplifyCFGOpt::hoistCommonCodeFromSuccessors`. That is for cases like ``` void test (int a, int *c, int *d) { if (a) *c = a; else *d = a; } ```
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llvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops-with-cf.ll
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py | ||
; RUN: opt < %s -mtriple=x86_64 -mattr=+cf -O1 -S | FileCheck %s | ||
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;; Test masked.load/store.v1* is generated in simplifycfg and not falls back to branch+load/store in following passes. | ||
define void @basic(i1 %cond, ptr %b, ptr %p, ptr %q) { | ||
; CHECK-LABEL: @basic( | ||
; CHECK-NEXT: entry: | ||
; CHECK-NEXT: [[TMP0:%.*]] = bitcast i1 [[COND:%.*]] to <1 x i1> | ||
; CHECK-NEXT: [[TMP1:%.*]] = call <1 x i16> @llvm.masked.load.v1i16.p0(ptr [[P:%.*]], i32 2, <1 x i1> [[TMP0]], <1 x i16> poison) | ||
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i16> [[TMP1]] to i16 | ||
; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i32> @llvm.masked.load.v1i32.p0(ptr [[Q:%.*]], i32 4, <1 x i1> [[TMP0]], <1 x i32> poison) | ||
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i32> [[TMP3]] to i32 | ||
; CHECK-NEXT: [[TMP5:%.*]] = call <1 x i64> @llvm.masked.load.v1i64.p0(ptr [[B:%.*]], i32 8, <1 x i1> [[TMP0]], <1 x i64> poison) | ||
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[TMP5]] to i64 | ||
; CHECK-NEXT: [[TMP7:%.*]] = bitcast i16 [[TMP2]] to <1 x i16> | ||
; CHECK-NEXT: call void @llvm.masked.store.v1i16.p0(<1 x i16> [[TMP7]], ptr [[B]], i32 2, <1 x i1> [[TMP0]]) | ||
; CHECK-NEXT: [[TMP8:%.*]] = bitcast i32 [[TMP4]] to <1 x i32> | ||
; CHECK-NEXT: call void @llvm.masked.store.v1i32.p0(<1 x i32> [[TMP8]], ptr [[P]], i32 4, <1 x i1> [[TMP0]]) | ||
; CHECK-NEXT: [[TMP9:%.*]] = bitcast i64 [[TMP6]] to <1 x i64> | ||
; CHECK-NEXT: call void @llvm.masked.store.v1i64.p0(<1 x i64> [[TMP9]], ptr [[Q]], i32 8, <1 x i1> [[TMP0]]) | ||
; CHECK-NEXT: ret void | ||
; | ||
entry: | ||
br i1 %cond, label %if.true, label %if.false | ||
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if.false: | ||
br label %if.end | ||
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if.true: | ||
%pv = load i16, ptr %p, align 2 | ||
%qv = load i32, ptr %q, align 4 | ||
%bv = load i64, ptr %b, align 8 | ||
store i16 %pv, ptr %b, align 2 | ||
store i32 %qv, ptr %p, align 4 | ||
store i64 %bv, ptr %q, align 8 | ||
br label %if.false | ||
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if.end: | ||
ret void | ||
} |
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