Implements 32bits MIPS with verilog. (18.11.25 ~ 18.12.)
add, addi, sub, and, or, slt, lw, sw, beq, j, SYSCALL(partial)
0 > Inner Program running
1 > MIPS Interpreter mode
0 > current instruction
1 > register value
1-9, a-f > for hex input (instruction used by interpreter mode)
s : start > start inner program or interpreter
r : resume > back to INIT state (when interpreter)
TeamI_21400337_박천명_21400404_신다현.pdf
Please check appendix of doc