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1. TIDENet TIDENet Public

   TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google SkyWater PDK, OpenLANE, and Caravel.

   VHDL 17 5

2. FPGA-Placement-Generator FPGA-Placement-Generator Public

   This tool generates a macro_placement.cfg file for use with OpenLANE and OpenFPGA.

   Verilog 2

3. FPGA_core_generator FPGA_core_generator Public

   Generates a valid fpga_core hardware description based on input fpga_top.v

   Python 1

4. OpenRAM-sky130 OpenRAM-sky130 Public

   Forked from VLSIDA/OpenRAM

   Fork of OpenRAM including skywater130 technology files for OOTB compatibility with skywater. Otherwise, direct from upstream.

   Python

5. C-port-scanner C-port-scanner Public

   A very lightweight port scanner in C for the class "Intro to Cybersecurity"

   C