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peripherals.h clean and duplicates removal #1599

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merged 3 commits into from
Aug 23, 2023
Merged

peripherals.h clean and duplicates removal #1599

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76b2d06
init
briskspirit Aug 21, 2023
3730485
ULPI disable
briskspirit Aug 22, 2023
3da7d26
not related to clocks
briskspirit Aug 23, 2023
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23 changes: 15 additions & 8 deletions board/stm32fx/peripherals.h
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Original file line number Diff line number Diff line change
Expand Up @@ -55,13 +55,20 @@ void flasher_peripherals_init(void) {

// Peripheral initialization
void peripherals_init(void) {
// enable GPIOB, UART2, CAN, USB clock
// enable GPIO(A,B,C,D)
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN;

// Supplemental
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
RCC->APB1ENR |= RCC_APB1ENR_PWREN; // for RTC config
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;

// Connectivity
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
RCC->APB1ENR |= RCC_APB1ENR_USART3EN;
#ifndef PEDAL
Expand All @@ -72,20 +79,20 @@ void peripherals_init(void) {
#ifdef CAN3
RCC->APB1ENR |= RCC_APB1ENR_CAN3EN;
#endif

// Analog
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
RCC->APB1ENR |= RCC_APB1ENR_DACEN;

// Timers
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // clock source timer
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // main counter
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // pedal and fan PWM
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // IR PWM
RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; // k-line init
RCC->APB1ENR |= RCC_APB1ENR_TIM6EN; // interrupt timer
RCC->APB1ENR |= RCC_APB1ENR_TIM12EN; // gmlan_alt
RCC->APB1ENR |= RCC_APB1ENR_PWREN; // for RTC config
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // clock source timer
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
RCC->APB2ENR |= RCC_APB2ENR_TIM9EN; // slow loop
RCC->APB1ENR |= RCC_APB1ENR_TIM12EN; // gmlan_alt
}

void enable_interrupt_timer(void) {
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7 changes: 0 additions & 7 deletions board/stm32h7/clock.h
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Original file line number Diff line number Diff line change
Expand Up @@ -56,9 +56,6 @@ void clock_init(void) {
// Set SysClock source to PLL
register_set(&(RCC->CFGR), RCC_CFGR_SW_PLL1, 0x7U);
while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL1);

// SYSCFG peripheral clock enable
register_set_bits(&(RCC->AHB4ENR), RCC_APB4ENR_SYSCFGEN);
//////////////END OTHER CLOCKS////////////////////

// Configure clock source for USB (HSI48)
Expand All @@ -71,8 +68,4 @@ void clock_init(void) {
register_set_bits(&(RCC->CR), RCC_CR_CSSHSEON);
//Enable Vdd33usb supply level detector
register_set_bits(&(PWR->CR3), PWR_CR3_USB33DEN);

// Enable CPU access to SRAM1 and SRAM2 (in domain D2)
register_set_bits(&(RCC->AHB2ENR), RCC_AHB2ENR_SRAM1EN);
register_set_bits(&(RCC->AHB2ENR), RCC_AHB2ENR_SRAM2EN);
}
36 changes: 21 additions & 15 deletions board/stm32h7/peripherals.h
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Original file line number Diff line number Diff line change
Expand Up @@ -110,34 +110,40 @@ void peripherals_init(void) {
RCC->AHB4ENR |= RCC_AHB4ENR_GPIOFEN;
RCC->AHB4ENR |= RCC_AHB4ENR_GPIOGEN;

RCC->APB2ENR |= RCC_APB2ENR_SPI4EN; // SPI
// Enable CPU access to SRAM1 and SRAM2 (in domain D2) for DMA
RCC->AHB2ENR |= RCC_AHB2ENR_SRAM1EN | RCC_AHB2ENR_SRAM2EN;

// Supplemental
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; // DAC DMA
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; // SPI DMA
RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN;

// Connectivity
RCC->APB2ENR |= RCC_APB2ENR_SPI4EN; // SPI
RCC->APB1LENR |= RCC_APB1LENR_I2C5EN; // codec I2C
RCC->AHB1ENR |= RCC_AHB1ENR_USB1OTGHSEN; // USB
RCC->AHB1LPENR |= RCC_AHB1LPENR_USB1OTGHSLPEN; // USB LP needed for CSleep state(__WFI())
RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_USB1OTGHSULPILPEN); // disable USB ULPI
RCC->APB1LENR |= RCC_APB1LENR_UART7EN; // SOM uart
RCC->APB1HENR |= RCC_APB1HENR_FDCANEN; // FDCAN core enable

// Analog
RCC->AHB1ENR |= RCC_AHB1ENR_ADC12EN; // Enable ADC12 clocks
RCC->APB1LENR |= RCC_APB1LENR_DAC12EN; // DAC

// Timers
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // clock source timer
RCC->APB1LENR |= RCC_APB1LENR_TIM2EN; // main counter
RCC->APB1LENR |= RCC_APB1LENR_TIM3EN; // fan pwm
RCC->APB1LENR |= RCC_APB1LENR_TIM6EN; // interrupt timer
RCC->APB1LENR |= RCC_APB1LENR_TIM7EN; // DMA trigger timer
RCC->APB1LENR |= RCC_APB1LENR_UART7EN; // SOM uart
RCC->APB1LENR |= RCC_APB1LENR_DAC12EN; // DAC
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN; // tick timer
RCC->APB1LENR |= RCC_APB1LENR_TIM12EN; // slow loop
RCC->APB1LENR |= RCC_APB1LENR_I2C5EN; // codec I2C
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // clock source timer

RCC->APB1HENR |= RCC_APB1HENR_FDCANEN; // FDCAN core enable
RCC->AHB1ENR |= RCC_AHB1ENR_ADC12EN; // Enable ADC12 clocks

RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN;

#ifdef PANDA_JUNGLE
RCC->AHB3ENR |= RCC_AHB3ENR_SDMMC1EN; // SDMMC
RCC->AHB4ENR |= RCC_AHB4ENR_ADC3EN; // Enable ADC3 clocks
#endif

// HS USB enable, also LP is needed for CSleep state(__WFI())
RCC->AHB1ENR |= RCC_AHB1ENR_USB1OTGHSEN;
RCC->AHB1LPENR |= RCC_AHB1LPENR_USB1OTGHSLPEN;
RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_USB1OTGHSULPILPEN);
}

void enable_interrupt_timer(void) {
Expand Down