rv64: implement instructions sets I, Zifenci, Zicsr, M, A, F, D, B

core-lang · Oct 15, 2023 · d6a6162 · d6a6162
1 parent 7b79414
commit d6a6162
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diff --git a/dora-asm/src/lib.rs b/dora-asm/src/lib.rs
@@ -1,6 +1,7 @@
 use byteorder::{LittleEndian, WriteBytesExt};
 
 pub mod arm64;
+pub mod rv64;
 pub mod x64;
 
 use std::convert::TryInto;