Added support for Tiger Lake (Intel ME 15)

corna · Jul 24, 2022 · 3f1b919 · 3f1b919
1 parent 392cb43
commit 3f1b919
Showing 1 changed file with 18 additions and 0 deletions.
diff --git a/me_cleaner.py b/me_cleaner.py
@@ -47,6 +47,7 @@
     "986a78e481f185f7d54e4af06eb413f6": ("ME",  ("11.x.x.x",)),
     "3efc26920b4bee901b624771c742887b": ("ME",  ("12.x.x.x",)),
     "8e4f834644da2bef03039d69d41ecf02": ("ME",  ("14.x.x.x",)),
+    "b29411f89bf20ed177d411c46e8ec185": ("ME",  ("15.x.x.x",)),
     "bda0b6bb8ca0bf0cac55ac4c4d55e0f2": ("TXE", ("1.x.x.x",)),
     "b726a2ab9cd59d4e62fe2bead7cf6997": ("TXE", ("1.x.x.x",)),
     "0633d7f951a3e7968ae7460861be9cfb": ("TXE", ("2.x.x.x",)),
@@ -664,6 +665,12 @@ def start_end_to_flreg(start, end):
             num_entries = unpack("<I", mef.read(4))[0]
 
             mef.seek(ftpr_offset + 0x10)
+            data = mef.read(0x18)
+
+            ## Intel ME version 15 seems to have 4 more bytes ##
+            if data[0] >= 128:
+                mef.seek(ftpr_offset + 0x14)
+
             ftpr_mn2_offset = -1
 
             for i in range(0, num_entries):
@@ -695,6 +702,8 @@ def start_end_to_flreg(start, end):
             gen = 4
         elif version[0] == 14:
             gen = 5
+        elif version[0] == 15:
+            gen = 6
 
         print("ME/TXE firmware version {} (generation {})"
               .format('.'.join(str(i) for i in version), gen))
@@ -755,6 +764,11 @@ def start_end_to_flreg(start, end):
             pchstrp32 = unpack("<I", fdf.read(4))[0]
             print("The HAP bit is " +
                   ("SET" if pchstrp32 & 1 << 16 else "NOT SET"))
+        elif gen == 6:
+            fdf.seek(fpsba + 0x7C)
+            pchstrp31 = unpack("<I", fdf.read(4))[0]
+            print("The HAP bit is " +
+                  ("SET" if pchstrp31 & 1 << 16 else "NOT SET"))
         else:
             fdf.seek(fpsba)
             pchstrp0 = unpack("<I", fdf.read(4))[0]
@@ -921,6 +935,10 @@ def start_end_to_flreg(start, end):
                 print("Setting the HAP bit in PCHSTRP32 to disable Intel ME...")
                 pchstrp32 |= (1 << 16)
                 fdf.write_to(fpsba + 0x80, pack("<I", pchstrp32))
+            elif gen == 6:
+                print("Setting the HAP bit in PCHSTRP31 to disable Intel ME...")
+                pchstrp31 |= (1 << 16)
+                fdf.write_to(fpsba + 0x7C, pack("<I", pchstrp31))
             else:
                 print("Setting the AltMeDisable bit in PCHSTRP10 to disable "
                       "Intel ME...")