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[RISCV] Implement RV64D codegen
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This patch:
* Adds necessary RV64D codegen patterns
* Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI)

Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type.

Differential Revision: https://reviews.llvm.org/D53237

llvm-svn: 352833
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@asb @Disasm
asb authored and Disasm committed Feb 11, 2019
1 parent c6aca6d commit 70b9bc4
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Showing 13 changed files with 1,513 additions and 4 deletions.
11 changes: 7 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -936,6 +936,10 @@ static bool CC_RISCV(const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT,
LocVT = XLenVT;
LocInfo = CCValAssign::BCvt;
}
if (XLen == 64 && ValVT == MVT::f64) {
LocVT = MVT::i64;
LocInfo = CCValAssign::BCvt;
}

// Any return value split in to more than two values can't be returned
// directly.
Expand Down Expand Up @@ -1043,8 +1047,9 @@ static bool CC_RISCV(const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT,
return false;
}

if (ValVT == MVT::f32) {
LocVT = MVT::f32;
// When an f32 or f64 is passed on the stack, no bit-conversion is needed.
if (ValVT == MVT::f32 || ValVT == MVT::f64) {
LocVT = ValVT;
LocInfo = CCValAssign::Full;
}
State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
Expand Down Expand Up @@ -1179,8 +1184,6 @@ static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain,
ExtType = ISD::NON_EXTLOAD;
break;
}
if (ValVT == MVT::f32)
LocVT = MVT::f32;
Val = DAG.getExtLoad(
ExtType, DL, LocVT, Chain, FIN,
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), ValVT);
Expand Down
23 changes: 23 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoD.td
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Original file line number Diff line number Diff line change
Expand Up @@ -308,3 +308,26 @@ def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_WU_D FPR64:$rs1, 0b001)>;
def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_W GPR:$rs1)>;
def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_WU GPR:$rs1)>;
} // Predicates = [HasStdExtD, IsRV32]

let Predicates = [HasStdExtD, IsRV64] in {
def : Pat<(bitconvert GPR:$rs1), (FMV_D_X GPR:$rs1)>;
def : Pat<(bitconvert FPR64:$rs1), (FMV_X_D FPR64:$rs1)>;

// FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
// because fpto[u|s]i produce poison if the value can't fit into the target.
// We match the single case below because fcvt.wu.d sign-extends its result so
// is cheaper than fcvt.lu.d+sext.w.
def : Pat<(sext_inreg (zexti32 (fp_to_uint FPR64:$rs1)), i32),
(FCVT_WU_D $rs1, 0b001)>;

// [u]int32->fp
def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_D_W $rs1)>;
def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_D_WU $rs1)>;

def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_L_D FPR64:$rs1, 0b001)>;
def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_LU_D FPR64:$rs1, 0b001)>;

// [u]int64->fp. Match GCC and default to using dynamic rounding mode.
def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_L GPR:$rs1, 0b111)>;
def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_LU GPR:$rs1, 0b111)>;
} // Predicates = [HasStdExtD, IsRV64]
167 changes: 167 additions & 0 deletions llvm/test/CodeGen/RISCV/double-arith.ll
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Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s

; These tests are each targeted at a particular RISC-V FPU instruction. Most
; other files in this folder exercise LLVM IR instructions that don't directly
Expand All @@ -22,6 +24,14 @@ define double @fadd_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fadd_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = fadd double %a, %b
ret double %1
}
Expand All @@ -42,6 +52,14 @@ define double @fsub_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fsub_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fsub.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = fsub double %a, %b
ret double %1
}
Expand All @@ -62,6 +80,14 @@ define double @fmul_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fmul_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fmul.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = fmul double %a, %b
ret double %1
}
Expand All @@ -82,6 +108,14 @@ define double @fdiv_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fdiv_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fdiv.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = fdiv double %a, %b
ret double %1
}
Expand All @@ -101,6 +135,13 @@ define double @fsqrt_d(double %a) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fsqrt_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fsqrt.d ft0, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = call double @llvm.sqrt.f64(double %a)
ret double %1
}
Expand All @@ -123,6 +164,14 @@ define double @fsgnj_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fsgnj_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fsgnj.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = call double @llvm.copysign.f64(double %a, double %b)
ret double %1
}
Expand All @@ -141,6 +190,14 @@ define i32 @fneg_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: feq.d a0, ft0, ft1
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fneg_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fadd.d ft0, ft0, ft0
; RV64IFD-NEXT: fneg.d ft1, ft0
; RV64IFD-NEXT: feq.d a0, ft0, ft1
; RV64IFD-NEXT: ret
%1 = fadd double %a, %a
%2 = fneg double %1
%3 = fcmp oeq double %1, %2
Expand All @@ -149,6 +206,9 @@ define i32 @fneg_d(double %a, double %b) nounwind {
}

define double @fsgnjn_d(double %a, double %b) nounwind {
; TODO: fsgnjn.s isn't selected on RV64 because DAGCombiner::visitBITCAST will
; convert (bitconvert (fneg x)) to a xor.
;
; RV32IFD-LABEL: fsgnjn_d:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
Expand All @@ -164,6 +224,17 @@ define double @fsgnjn_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fsgnjn_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi a2, zero, -1
; RV64IFD-NEXT: slli a2, a2, 63
; RV64IFD-NEXT: xor a1, a1, a2
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fsgnj.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = fsub double -0.0, %b
%2 = call double @llvm.copysign.f64(double %a, double %1)
ret double %2
Expand Down Expand Up @@ -191,6 +262,16 @@ define double @fabs_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fabs_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fabs.d ft1, ft0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = fadd double %a, %b
%2 = call double @llvm.fabs.f64(double %1)
%3 = fadd double %2, %1
Expand All @@ -215,6 +296,14 @@ define double @fmin_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fmin_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fmin.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = call double @llvm.minnum.f64(double %a, double %b)
ret double %1
}
Expand All @@ -237,6 +326,14 @@ define double @fmax_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fmax_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fmax.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = call double @llvm.maxnum.f64(double %a, double %b)
ret double %1
}
Expand All @@ -254,6 +351,13 @@ define i32 @feq_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: feq_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: ret
%1 = fcmp oeq double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -272,6 +376,13 @@ define i32 @flt_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: flt_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: ret
%1 = fcmp olt double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -290,6 +401,13 @@ define i32 @fle_d(double %a, double %b) nounwind {
; RV32IFD-NEXT: fle.d a0, ft1, ft0
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fle_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: ret
%1 = fcmp ole double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -316,6 +434,15 @@ define double @fmadd_d(double %a, double %b, double %c) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fmadd_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmv.d.x ft2, a0
; RV64IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = call double @llvm.fma.f64(double %a, double %b, double %c)
ret double %1
}
Expand Down Expand Up @@ -343,6 +470,19 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fmsub_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: lui a2, %hi(.LCPI15_0)
; RV64IFD-NEXT: addi a2, a2, %lo(.LCPI15_0)
; RV64IFD-NEXT: fld ft1, 0(a2)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmv.d.x ft2, a0
; RV64IFD-NEXT: fmsub.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%c_ = fadd double 0.0, %c ; avoid negation using xor
%negc = fsub double -0.0, %c_
%1 = call double @llvm.fma.f64(double %a, double %b, double %negc)
Expand Down Expand Up @@ -373,6 +513,20 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmadd_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: lui a2, %hi(.LCPI16_0)
; RV64IFD-NEXT: addi a2, a2, %lo(.LCPI16_0)
; RV64IFD-NEXT: fld ft1, 0(a2)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.d.x ft2, a0
; RV64IFD-NEXT: fadd.d ft1, ft2, ft1
; RV64IFD-NEXT: fmv.d.x ft2, a1
; RV64IFD-NEXT: fnmadd.d ft0, ft1, ft2, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%a_ = fadd double 0.0, %a
%c_ = fadd double 0.0, %c
%nega = fsub double -0.0, %a_
Expand Down Expand Up @@ -404,6 +558,19 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind {
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmsub_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: lui a0, %hi(.LCPI17_0)
; RV64IFD-NEXT: addi a0, a0, %lo(.LCPI17_0)
; RV64IFD-NEXT: fld ft1, 0(a0)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.d.x ft1, a2
; RV64IFD-NEXT: fmv.d.x ft2, a1
; RV64IFD-NEXT: fnmsub.d ft0, ft0, ft2, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%a_ = fadd double 0.0, %a
%nega = fsub double -0.0, %a_
%1 = call double @llvm.fma.f64(double %nega, double %b, double %c)
Expand Down
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