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[AArch64] Display, export Floating-point Control Register FPCR
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@cyring
cyring committed Dec 4, 2024
1 parent cb4983a commit 56d46c2
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Showing 11 changed files with 87 additions and 34 deletions.
1 change: 1 addition & 0 deletions aarch64/corefreq-api.h
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Expand Up @@ -205,6 +205,7 @@ typedef struct
Bit64 SCTLR2 __attribute__ ((aligned (8)));
Bit64 EL __attribute__ ((aligned (8)));
Bit64 FPSR __attribute__ ((aligned (8)));
Bit64 FPCR __attribute__ ((aligned (8)));
Bit64 SVCR __attribute__ ((aligned (8)));
Bit64 CPACR __attribute__ ((aligned (8)));
} SystemRegister;
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4 changes: 4 additions & 0 deletions aarch64/corefreq-cli-json.c
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Expand Up @@ -1411,6 +1411,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
json_key(&s, "FPSR");
json_string(&s, hexStr);

snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.FPCR);
json_key(&s, "FPCR");
json_string(&s, hexStr);

snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.SVCR);
json_key(&s, "SVCR");
json_string(&s, hexStr);
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10 changes: 10 additions & 0 deletions aarch64/corefreq-cli-rsc-en.h
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Expand Up @@ -828,6 +828,13 @@
#define RSC_SYS_REG_FPSR_DZC_CODE_EN " Divide by Zero Cumulative "
#define RSC_SYS_REG_FPSR_IOC_CODE_EN " Invalid Operation Cumulative "

#define RSC_SYS_REG_FPCR_CODE_EN " Floating-point Control Register "
#define RSC_SYS_REG_FPCR_AHP_CODE_EN " Alternative Half-Precision "
#define RSC_SYS_REG_FPCR_DN_CODE_EN " Default NaN "
#define RSC_SYS_REG_FPCR_FZ_CODE_EN " Flush-to-Zero mode "
#define RSC_SYS_REG_FPCR_RM_CODE_EN " Rounding Mode "
#define RSC_SYS_REG_FPCR_FZH_CODE_EN " Flush-to-Zero on Half-precision "

#define RSC_SYS_REG_EL_CODE_EN " Exception Level "
#define RSC_SYS_REG_EL_EXEC_CODE_EN " Executes in AArch64 or AArch32 "
#define RSC_SYS_REG_EL_SEC_CODE_EN " Secure Exception Level "
Expand Down Expand Up @@ -2076,6 +2083,9 @@
#define RSC_SYS_REG_HDR_FPSR_CODE \
"FPSR\0 N \0 Z \0 C \0 V \0 QC \0 IDC\0 IXC\0 UFC\0 OFC\0 DZC\0 IOC"

#define RSC_SYS_REG_HDR_FPCR_CODE \
"FPCR\0 AHP\0 DN \0 FZ \0 RM \0 FZH"

#define RSC_SYS_REG_HDR11_EL_CODE \
" EL \0 \0"" Lev\0el0 \0 \0 Lev\0el1 \0 \0" \
" L\0evel\0""2 \0 \0 Lev\0el3 "
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7 changes: 7 additions & 0 deletions aarch64/corefreq-cli-rsc-fr.h
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Expand Up @@ -520,6 +520,13 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_SYS_REG_FPSR_DZC_CODE_FR RSC_SYS_REG_FPSR_DZC_CODE_EN
#define RSC_SYS_REG_FPSR_IOC_CODE_FR RSC_SYS_REG_FPSR_IOC_CODE_EN

#define RSC_SYS_REG_FPCR_CODE_FR RSC_SYS_REG_FPCR_CODE_EN
#define RSC_SYS_REG_FPCR_AHP_CODE_FR RSC_SYS_REG_FPCR_AHP_CODE_EN
#define RSC_SYS_REG_FPCR_DN_CODE_FR RSC_SYS_REG_FPCR_DN_CODE_EN
#define RSC_SYS_REG_FPCR_FZ_CODE_FR RSC_SYS_REG_FPCR_FZ_CODE_EN
#define RSC_SYS_REG_FPCR_RM_CODE_FR RSC_SYS_REG_FPCR_RM_CODE_EN
#define RSC_SYS_REG_FPCR_FZH_CODE_FR RSC_SYS_REG_FPCR_FZH_CODE_EN

#define RSC_SYS_REG_EL_CODE_FR RSC_SYS_REG_EL_CODE_EN
#define RSC_SYS_REG_EL_EXEC_CODE_FR RSC_SYS_REG_EL_EXEC_CODE_EN
#define RSC_SYS_REG_EL_SEC_CODE_FR RSC_SYS_REG_EL_SEC_CODE_EN
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7 changes: 7 additions & 0 deletions aarch64/corefreq-cli-rsc.c
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Expand Up @@ -728,6 +728,13 @@ RESOURCE_ST Resource[] = {
LDT(RSC_SYS_REG_FPSR_OFC),
LDT(RSC_SYS_REG_FPSR_DZC),
LDT(RSC_SYS_REG_FPSR_IOC),
LDQ(RSC_SYS_REG_HDR_FPCR),
LDT(RSC_SYS_REG_FPCR),
LDT(RSC_SYS_REG_FPCR_AHP),
LDT(RSC_SYS_REG_FPCR_DN),
LDT(RSC_SYS_REG_FPCR_FZ),
LDT(RSC_SYS_REG_FPCR_RM),
LDT(RSC_SYS_REG_FPCR_FZH),
LDQ(RSC_SYS_REG_HDR11_EL),
LDQ(RSC_SYS_REG_HDR12_EL),
LDT(RSC_SYS_REG_EL),
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7 changes: 7 additions & 0 deletions aarch64/corefreq-cli-rsc.h
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Expand Up @@ -551,6 +551,13 @@ enum {
RSC_SYS_REG_FPSR_OFC,
RSC_SYS_REG_FPSR_DZC,
RSC_SYS_REG_FPSR_IOC,
RSC_SYS_REG_HDR_FPCR,
RSC_SYS_REG_FPCR,
RSC_SYS_REG_FPCR_AHP,
RSC_SYS_REG_FPCR_DN,
RSC_SYS_REG_FPCR_FZ,
RSC_SYS_REG_FPCR_RM,
RSC_SYS_REG_FPCR_FZH,
RSC_SYS_REG_HDR11_EL,
RSC_SYS_REG_HDR12_EL,
RSC_SYS_REG_EL,
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73 changes: 39 additions & 34 deletions aarch64/corefreq-cli.c
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Expand Up @@ -453,7 +453,7 @@ REASON_CODE SystemRegisters( Window *win,
};
enum AUTOMAT {
DO_END, DO_SPC, DO_CPU, DO_FLAG, DO_HCR,
DO_SCTLR, DO_SCTLR2, DO_EL, DO_FPSR, DO_ACR
DO_SCTLR, DO_SCTLR2, DO_EL, DO_FPSR, DO_FPCR, DO_ACR
};
const struct SR_ST {
struct SR_HDR {
Expand Down Expand Up @@ -1064,43 +1064,43 @@ REASON_CODE SystemRegisters( Window *win,
},
{
.header = (struct SR_HDR[]) {
[ 0] = {&RSC(SYS_REG_HDR_CPACR).CODE()[ 0],RSC(SYS_REG_CPACR).CODE()},
[ 1] = {&RSC(SYS_REG_HDR_CPACR).CODE()[ 5],RSC(SYS_REG_ACR_TCP).CODE()},
[ 2] = {&RSC(SYS_REG_HDR_CPACR).CODE()[10],RSC(SYS_REG_ACR_TAM).CODE()},
[ 3] = {&RSC(SYS_REG_HDR_CPACR).CODE()[15],RSC(SYS_REG_ACR_POE).CODE()},
[ 4] = {&RSC(SYS_REG_HDR_CPACR).CODE()[20],RSC(SYS_REG_ACR_TTA).CODE()},
[ 5] = {&RSC(SYS_REG_HDR_CPACR).CODE()[25],RSC(SYS_REG_ACR_SME).CODE()},
[ 6] = {&RSC(SYS_REG_HDR_CPACR).CODE()[30],RSC(SYS_REG_ACR_FP).CODE()},
[ 7] = {&RSC(SYS_REG_HDR_CPACR).CODE()[35],RSC(SYS_REG_ACR_ZEN).CODE()},
[ 8] = {&RSC(SYS_REG_HDR_CPACR).CODE()[40],RSC(SYS_REG_ACR_R8).CODE()},
[ 9] = {&RSC(SYS_REG_HDR_CPACR).CODE()[45],RSC(SYS_REG_ACR_R0).CODE()},
[10] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[11] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[12] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[13] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[14] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[15] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[16] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[ 0] = {&RSC(SYS_REG_HDR_FPCR).CODE()[ 0],RSC(SYS_REG_FPCR).CODE()},
[ 1] = {&RSC(SYS_REG_HDR_FPCR).CODE()[ 5],RSC(SYS_REG_FPCR_AHP).CODE()},
[ 2] = {&RSC(SYS_REG_HDR_FPCR).CODE()[10],RSC(SYS_REG_FPCR_DN).CODE()},
[ 3] = {&RSC(SYS_REG_HDR_FPCR).CODE()[15],RSC(SYS_REG_FPCR_FZ).CODE()},
[ 4] = {&RSC(SYS_REG_HDR_FPCR).CODE()[20],RSC(SYS_REG_FPCR_RM).CODE()},
[ 5] = {&RSC(SYS_REG_HDR_FPCR).CODE()[25],RSC(SYS_REG_FPCR_FZH).CODE()},
[ 6] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[ 7] = {&RSC(SYS_REG_HDR_CPACR).CODE()[ 0],RSC(SYS_REG_CPACR).CODE()},
[ 8] = {&RSC(SYS_REG_HDR_CPACR).CODE()[ 5],RSC(SYS_REG_ACR_TCP).CODE()},
[ 9] = {&RSC(SYS_REG_HDR_CPACR).CODE()[10],RSC(SYS_REG_ACR_TAM).CODE()},
[10] = {&RSC(SYS_REG_HDR_CPACR).CODE()[15],RSC(SYS_REG_ACR_POE).CODE()},
[11] = {&RSC(SYS_REG_HDR_CPACR).CODE()[20],RSC(SYS_REG_ACR_TTA).CODE()},
[12] = {&RSC(SYS_REG_HDR_CPACR).CODE()[25],RSC(SYS_REG_ACR_SME).CODE()},
[13] = {&RSC(SYS_REG_HDR_CPACR).CODE()[30],RSC(SYS_REG_ACR_FP).CODE()},
[14] = {&RSC(SYS_REG_HDR_CPACR).CODE()[35],RSC(SYS_REG_ACR_ZEN).CODE()},
[15] = {&RSC(SYS_REG_HDR_CPACR).CODE()[40],RSC(SYS_REG_ACR_R8).CODE()},
[16] = {&RSC(SYS_REG_HDR_CPACR).CODE()[45],RSC(SYS_REG_ACR_R0).CODE()},
{NULL, NULL}
},
.flag = (struct SR_BIT[]) {
[ 0] = {DO_CPU , 1 , UNDEF_CR , 0 },
[ 1] = {DO_ACR , 1 , ACR_TCPAC , 1 },
[ 2] = {DO_ACR , 1 , ACR_TAM , 1 },
[ 3] = {DO_ACR , 1 , ACR_E0POE , 1 },
[ 4] = {DO_ACR , 1 , ACR_TTA , 1 },
[ 5] = {DO_ACR , 1 , ACR_SMEN , 2 },
[ 6] = {DO_ACR , 1 , ACR_FPEN , 2 },
[ 7] = {DO_ACR , 1 , ACR_ZEN , 2 },
[ 8] = {DO_ACR , 1 , ACR_RES8 , 8 },
[ 9] = {DO_ACR , 1 , ACR_RES0 , 8 },
[10] = {DO_SPC , 1 , UNDEF_CR , 0 },
[11] = {DO_SPC , 1 , UNDEF_CR , 0 },
[12] = {DO_SPC , 1 , UNDEF_CR , 0 },
[13] = {DO_SPC , 1 , UNDEF_CR , 0 },
[14] = {DO_SPC , 1 , UNDEF_CR , 0 },
[15] = {DO_SPC , 1 , UNDEF_CR , 0 },
[16] = {DO_SPC , 1 , UNDEF_CR , 0 },
[ 1] = {DO_FPCR, 1 , FPCR_AHP , 1 },
[ 2] = {DO_FPCR, 1 , FPCR_DN , 1 },
[ 3] = {DO_FPCR, 1 , FPCR_FZ , 1 },
[ 4] = {DO_FPCR, 1 , FPCR_RM , 2 },
[ 5] = {DO_FPCR, 1 , FPCR_FZH , 1 },
[ 6] = {DO_SPC , 1 , UNDEF_CR , 0 },
[ 7] = {DO_CPU , 1 , UNDEF_CR , 0 },
[ 8] = {DO_ACR , 1 , ACR_TCPAC , 1 },
[ 9] = {DO_ACR , 1 , ACR_TAM , 1 },
[10] = {DO_ACR , 1 , ACR_E0POE , 1 },
[11] = {DO_ACR , 1 , ACR_TTA , 1 },
[12] = {DO_ACR , 1 , ACR_SMEN , 2 },
[13] = {DO_ACR , 1 , ACR_FPEN , 2 },
[14] = {DO_ACR , 1 , ACR_ZEN , 2 },
[15] = {DO_ACR , 1 , ACR_RES8 , 8 },
[16] = {DO_ACR , 1 , ACR_RES0 , 8 },
{DO_END , 1 , UNDEF_CR , 0 }
}
}
Expand Down Expand Up @@ -1177,6 +1177,11 @@ REASON_CODE SystemRegisters( Window *win,
BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.FPSR,
pFlag->pos, pFlag->len));
break;
case DO_FPCR:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.FPCR,
pFlag->pos, pFlag->len));
break;
case DO_ACR:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.CPACR,
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1 change: 1 addition & 0 deletions aarch64/corefreq.h
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Expand Up @@ -192,6 +192,7 @@ typedef struct
Bit64 SCTLR2 __attribute__ ((aligned (8)));
Bit64 EL __attribute__ ((aligned (8)));
Bit64 FPSR __attribute__ ((aligned (8)));
Bit64 FPCR __attribute__ ((aligned (8)));
Bit64 SVCR __attribute__ ((aligned (8)));
Bit64 CPACR __attribute__ ((aligned (8)));
} SystemRegister;
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3 changes: 3 additions & 0 deletions aarch64/corefreqd.c
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Expand Up @@ -875,6 +875,9 @@ void SystemRegisters( RO(SHM_STRUCT) *RO(Shm), RO(CORE) **RO(Core),
RO(Shm)->Cpu[cpu].SystemRegister.FPSR = \
RO(Core, AT(cpu))->SystemRegister.FPSR;

RO(Shm)->Cpu[cpu].SystemRegister.FPCR = \
RO(Core, AT(cpu))->SystemRegister.FPCR;

RO(Shm)->Cpu[cpu].SystemRegister.SVCR = \
RO(Core, AT(cpu))->SystemRegister.SVCR;

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2 changes: 2 additions & 0 deletions aarch64/corefreqk.c
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Expand Up @@ -2453,6 +2453,7 @@ static void SystemRegisters(CORE_RO *Core)
"mrs %[sctlr], sctlr_el1" "\n\t"
"mrs %[mmfr1], id_aa64mmfr1_el1""\n\t"
"mrs %[pfr0] , id_aa64pfr0_el1""\n\t"
"mrs %[fpcr] , fpcr" "\n\t"
"mrs %[fpsr] , fpsr" "\n\t"
"cmp xzr , xzr, lsl #0" "\n\t"
"mrs x14 , nzcv" "\n\t"
Expand All @@ -2467,6 +2468,7 @@ static void SystemRegisters(CORE_RO *Core)
: [sctlr] "=r" (Core->SystemRegister.SCTLR),
[mmfr1] "=r" (mmfr1),
[pfr0] "=r" (pfr0),
[fpcr] "=r" (Core->SystemRegister.FPCR),
[fpsr] "=r" (Core->SystemRegister.FPSR),
[flags] "=r" (Core->SystemRegister.FLAGS)
:
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6 changes: 6 additions & 0 deletions aarch64/coretypes.h
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Expand Up @@ -289,6 +289,12 @@ enum SYS_REG {
FPSR_DZC = 1,
FPSR_IOC = 0,

FPCR_AHP = 26,
FPCR_DN = 25,
FPCR_FZ = 24,
FPCR_RM = 22, /* [23:22] */
FPCR_FZH = 19,

ACR_TCPAC = 31,
ACR_TAM = 30,
ACR_E0POE = 29,
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