[AArch64] Renamed Microcode to Revision

cyring · Jan 28, 2024 · 75c68c7 · 75c68c7
1 parent 7021689
commit 75c68c7
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Showing 9 changed files with 11 additions and 11 deletions.
diff --git a/aarch64/corefreq-api.h b/aarch64/corefreq-api.h
@@ -187,7 +187,7 @@ typedef struct
 					IORedir :  2-1,  /* Core	*/
 					SCTLRX	:  3-2,  /* Thread	*/
 					Unused	: 32-3,
-					Microcode:64-32; /* Thread	*/
+					Revision: 64-32;
 		};
 		unsigned short int	CStateLimit;
 		unsigned short int	CStateBaseAddr; /* Any I/O BAR	*/

diff --git a/aarch64/corefreq-cli-rsc-en.h b/aarch64/corefreq-cli-rsc-en.h
@@ -625,7 +625,7 @@
 #define RSC_PROCESSOR_CODE_EN		"Processor"
 #define RSC_ARCHITECTURE_CODE_EN	"Architecture"
 #define RSC_VENDOR_ID_CODE_EN		"Vendor ID"
-#define RSC_MICROCODE_CODE_EN		"Microcode"
+#define RSC_REVISION_CODE_EN		"Revision"
 #define RSC_SIGNATURE_CODE_EN		"Signature"
 #define RSC_STEPPING_CODE_EN		"Stepping"
 #define RSC_ONLINE_CPU_CODE_EN		"Online CPU"

diff --git a/aarch64/corefreq-cli-rsc-fr.h b/aarch64/corefreq-cli-rsc-fr.h
@@ -321,7 +321,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 #define RSC_PROCESSOR_CODE_FR		"Processeur"
 #define RSC_ARCHITECTURE_CODE_FR	"Architecture"
 #define RSC_VENDOR_ID_CODE_FR		"ID vendeur"
-#define RSC_MICROCODE_CODE_FR		"Microcode"
+#define RSC_REVISION_CODE_FR		"R""\xa9""vision"
 #define RSC_SIGNATURE_CODE_FR		"Signature"
 #define RSC_STEPPING_CODE_FR		"Stepping"
 #define RSC_ONLINE_CPU_CODE_FR		"CPU en ligne"

diff --git a/aarch64/corefreq-cli-rsc.c b/aarch64/corefreq-cli-rsc.c
@@ -505,7 +505,7 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_ARCHITECTURE),
 	LDT(RSC_VENDOR_ID),
 	LDQ(RSC_HYBRID),
-	LDT(RSC_MICROCODE),
+	LDT(RSC_REVISION),
 	LDT(RSC_SIGNATURE),
 	LDT(RSC_STEPPING),
 	LDT(RSC_ONLINE_CPU),

diff --git a/aarch64/corefreq-cli-rsc.h b/aarch64/corefreq-cli-rsc.h
@@ -328,7 +328,7 @@ enum {
 	RSC_ARCHITECTURE,
 	RSC_VENDOR_ID,
 	RSC_HYBRID,
-	RSC_MICROCODE,
+	RSC_REVISION,
 	RSC_SIGNATURE,
 	RSC_STEPPING,
 	RSC_ONLINE_CPU,

diff --git a/aarch64/corefreq-cli.c b/aarch64/corefreq-cli.c
@@ -1054,9 +1054,9 @@ REASON_CODE SysInfoProc(Window *win,
 		hSpace, RO(Shm)->Proc.Features.Info.Vendor.ID );
 
 	PUT(	SCANKEY_NULL, attrib[0], width, 2,
-		"%s""%.*s[0x%08x]", RSC(MICROCODE).CODE(),
-		width - 15 - RSZ(MICROCODE), hSpace,
-		RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Query.Microcode );
+		"%s""%.*s[0x%08x]", RSC(REVISION).CODE(),
+		width - 15 - RSZ(REVISION), hSpace,
+		RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Query.Revision );
 
 	PUT(	SCANKEY_NULL, attrib[2], width, 2,
 		"%s""%.*s[%3X%1X_%1X%1X]", RSC(SIGNATURE).CODE(),

diff --git a/aarch64/corefreq.h b/aarch64/corefreq.h
@@ -33,7 +33,7 @@ typedef struct
 
 	struct
 	{
-		unsigned int		Microcode;
+		unsigned int		Revision;
 
 		struct {
 		unsigned short int	CfgLock :  1-0,

diff --git a/aarch64/corefreqd.c b/aarch64/corefreqd.c
@@ -1119,7 +1119,7 @@ void PerCore_Update(	RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc),
 	memcpy( RO(Shm)->Cpu[cpu].Boost, RO(Core, AT(cpu))->Boost,
 		(BOOST(SIZE)) * sizeof(unsigned int) );
 
-	RO(Shm)->Cpu[cpu].Query.Microcode = RO(Core, AT(cpu))->Query.Microcode;
+	RO(Shm)->Cpu[cpu].Query.Revision = RO(Core, AT(cpu))->Query.Revision;
 
 	Topology(RO(Shm), RO(Proc), RO(Core), cpu);
 

diff --git a/aarch64/corefreqk.c b/aarch64/corefreqk.c
@@ -1773,7 +1773,7 @@ static void PerCore_GenericMachine(void *arg)
 	cpupwrctl.value = read_sysreg_s(CPUPWRCTLR_EL1);
 	Core->Query.CStateBaseAddr = cpupwrctl.WFI_RET_CTRL;
     }
-	Core->Query.Microcode = revid.Revision;
+	Core->Query.Revision = revid.Revision;
 
 	SystemRegisters(Core);